[llvm] e5b23e5 - Autogen a test in advance of another change
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 22 19:38:54 PST 2021
Author: Philip Reames
Date: 2021-12-22T19:38:40-08:00
New Revision: e5b23e55a281646cd8ce85b24f5ac2d8a06cbef6
URL: https://github.com/llvm/llvm-project/commit/e5b23e55a281646cd8ce85b24f5ac2d8a06cbef6
DIFF: https://github.com/llvm/llvm-project/commit/e5b23e55a281646cd8ce85b24f5ac2d8a06cbef6.diff
LOG: Autogen a test in advance of another change
Added:
Modified:
llvm/test/Transforms/InstCombine/sink_sideeffecting_instruction.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/sink_sideeffecting_instruction.ll b/llvm/test/Transforms/InstCombine/sink_sideeffecting_instruction.ll
index e1d411c7a5a86..aed7db49b5fd2 100644
--- a/llvm/test/Transforms/InstCombine/sink_sideeffecting_instruction.ll
+++ b/llvm/test/Transforms/InstCombine/sink_sideeffecting_instruction.ll
@@ -1,12 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -instcombine -S < %s | FileCheck %s
; Function Attrs: noinline uwtable
define dso_local i32 @foo(i32* nocapture writeonly %arg) local_unnamed_addr #0 {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[VAR:%.*]] = call i32 @baz() #[[ATTR2:[0-9]+]]
+; CHECK-NEXT: store i32 [[VAR]], i32* [[ARG:%.*]], align 4, !tbaa [[TBAA0:![0-9]+]]
+; CHECK-NEXT: [[VAR1:%.*]] = call i32 @baz() #[[ATTR2]]
+; CHECK-NEXT: ret i32 [[VAR1]]
+;
bb:
- %tmp = call i32 @baz()
- store i32 %tmp, i32* %arg, align 4, !tbaa !2
- %tmp1 = call i32 @baz()
- ret i32 %tmp1
+ %var = call i32 @baz()
+ store i32 %var, i32* %arg, align 4, !tbaa !2
+ %var1 = call i32 @baz()
+ ret i32 %var1
}
declare dso_local i32 @baz() local_unnamed_addr
@@ -15,19 +23,19 @@ declare dso_local i32 @baz() local_unnamed_addr
; with out-params which are unused in the caller(test8). Note that foo is
; marked noinline to prevent IPO transforms.
; int foo();
-;
+;
; extern int foo(int *out) __attribute__((noinline));
; int foo(int *out) {
; *out = baz();
; return baz();
; }
-;
+;
; int test() {
-;
+;
; int notdead;
; if (foo(¬dead))
; return 0;
-;
+;
; int dead;
; int tmp = foo(&dead);
; if (notdead)
@@ -35,45 +43,71 @@ declare dso_local i32 @baz() local_unnamed_addr
; return bar();
; }
-; TODO: We should be able to sink the second call @foo at bb5 down to bb_crit_edge
+; TODO: We should be able to sink the second call @foo at bb5 down to bb_crit_edge
define dso_local i32 @test() local_unnamed_addr #2 {
-; CHECK-LABEL: test
-; CHECK: bb5:
-; CHECK: %tmp7 = call i32 @foo(i32* nonnull writeonly %tmp1)
-; CHECK-NEXT: br i1 %tmp9, label %bb10, label %bb_crit_edge
+; CHECK-LABEL: @test(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[VAR:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[VAR1:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[VAR2:%.*]] = bitcast i32* [[VAR]] to i8*
+; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[VAR2]])
+; CHECK-NEXT: [[VAR3:%.*]] = call i32 @foo(i32* nonnull writeonly [[VAR]])
+; CHECK-NEXT: [[VAR4:%.*]] = icmp eq i32 [[VAR3]], 0
+; CHECK-NEXT: br i1 [[VAR4]], label [[BB5:%.*]], label [[BB14:%.*]]
+; CHECK: bb5:
+; CHECK-NEXT: [[VAR6:%.*]] = bitcast i32* [[VAR1]] to i8*
+; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[VAR6]])
+; CHECK-NEXT: [[VAR8:%.*]] = load i32, i32* [[VAR]], align 4, !tbaa [[TBAA0]]
+; CHECK-NEXT: [[VAR9:%.*]] = icmp eq i32 [[VAR8]], 0
+; CHECK-NEXT: [[VAR7:%.*]] = call i32 @foo(i32* nonnull writeonly [[VAR1]])
+; CHECK-NEXT: br i1 [[VAR9]], label [[BB10:%.*]], label [[BB_CRIT_EDGE:%.*]]
+; CHECK: bb10:
+; CHECK-NEXT: [[VAR11:%.*]] = call i32 @bar()
+; CHECK-NEXT: br label [[BB12:%.*]]
+; CHECK: bb_crit_edge:
+; CHECK-NEXT: br label [[BB12]]
+; CHECK: bb12:
+; CHECK-NEXT: [[VAR13:%.*]] = phi i32 [ [[VAR11]], [[BB10]] ], [ [[VAR7]], [[BB_CRIT_EDGE]] ]
+; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[VAR6]])
+; CHECK-NEXT: br label [[BB14]]
+; CHECK: bb14:
+; CHECK-NEXT: [[VAR15:%.*]] = phi i32 [ [[VAR13]], [[BB12]] ], [ 0, [[BB:%.*]] ]
+; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[VAR2]])
+; CHECK-NEXT: ret i32 [[VAR15]]
+;
bb:
- %tmp = alloca i32, align 4
- %tmp1 = alloca i32, align 4
- %tmp2 = bitcast i32* %tmp to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp2) #4
- %tmp3 = call i32 @foo(i32* nonnull writeonly %tmp)
- %tmp4 = icmp eq i32 %tmp3, 0
- br i1 %tmp4, label %bb5, label %bb14
+ %var = alloca i32, align 4
+ %var1 = alloca i32, align 4
+ %var2 = bitcast i32* %var to i8*
+ call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %var2) #4
+ %var3 = call i32 @foo(i32* nonnull writeonly %var)
+ %var4 = icmp eq i32 %var3, 0
+ br i1 %var4, label %bb5, label %bb14
bb5: ; preds = %bb
- %tmp6 = bitcast i32* %tmp1 to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp6) #4
- %tmp8 = load i32, i32* %tmp, align 4, !tbaa !2
- %tmp9 = icmp eq i32 %tmp8, 0
- %tmp7 = call i32 @foo(i32* nonnull writeonly %tmp1)
- br i1 %tmp9, label %bb10, label %bb_crit_edge
+ %var6 = bitcast i32* %var1 to i8*
+ call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %var6) #4
+ %var8 = load i32, i32* %var, align 4, !tbaa !2
+ %var9 = icmp eq i32 %var8, 0
+ %var7 = call i32 @foo(i32* nonnull writeonly %var1)
+ br i1 %var9, label %bb10, label %bb_crit_edge
bb10: ; preds = %bb5
- %tmp11 = call i32 @bar()
+ %var11 = call i32 @bar()
br label %bb12
bb_crit_edge:
br label %bb12
bb12: ; preds = %bb10, %bb5
- %tmp13 = phi i32 [ %tmp11, %bb10 ], [ %tmp7, %bb_crit_edge ]
- call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp6) #4
+ %var13 = phi i32 [ %var11, %bb10 ], [ %var7, %bb_crit_edge ]
+ call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %var6) #4
br label %bb14
bb14: ; preds = %bb12, %bb
- %tmp15 = phi i32 [ %tmp13, %bb12 ], [ 0, %bb ]
- call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp2)
- ret i32 %tmp15
+ %var15 = phi i32 [ %var13, %bb12 ], [ 0, %bb ]
+ call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %var2)
+ ret i32 %var15
}
declare i32 @bar()
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