[PATCH] D116156: [AArch64] Adding "armv8.8-a" BC instruction.

[Tomas Matheson via Phabricator via llvm-commits]

tmatheson created this revision.
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'BC.cc', where 'cc' is any ordinary condition code, is an instruction
that looks exactly like B.cc (the normal conditional branch), except
that bit 4 of the encoding is 1 rather than 0, which hints something
to the branch predictor (specifically, that this branch is expected to
be highly consistent, even though _which way_ it will consistently go
is not known at compile time).

This commit introduces a special subtarget feature for HBC, which is a
dependency of the top-level 8.8-A feature, and uses that to enable the
new BC instruction.

Patch by Simon Tatham and Tomas Matheson


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116156

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/test/MC/AArch64/armv8.8a-hbc.s
  llvm/test/MC/Disassembler/AArch64/armv8.8a-hbc.txt

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