[PATCH] D113798: Add loop unrolling and peeling preferences for RISCV
Zixuan Wu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 22 01:55:11 PST 2021
zixuan-wu added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp:175
+ bool UseDefaultPreferences = true;
+ if (ST->getTuneCPU().contains("sifive-e76") ||
+ ST->getTuneCPU().contains("sifive-s76") ||
----------------
It's not a general principle to just enumerate tune cpus. Could we predict some feature or parameter from subtarget such as whether it's out-of-order. Or we need get UseDefaultPreferences value which has been initialized in subtarget directly.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D113798/new/
https://reviews.llvm.org/D113798
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