[PATCH] D113798: Add loop unrolling and peeling preferences for RISCV

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp:175
+  bool UseDefaultPreferences = true;
+  if (ST->getTuneCPU().contains("sifive-e76") ||
+      ST->getTuneCPU().contains("sifive-s76") ||
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It's not a general principle to just enumerate tune cpus. Could we predict some feature or parameter from subtarget such as whether it's out-of-order. Or we need get UseDefaultPreferences value which has been initialized in subtarget directly. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113798/new/

https://reviews.llvm.org/D113798