[PATCH] D116039: [X86] Combine reduce (add (mul x, y)) to VNNI instruction.

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 21 23:32:52 PST 2021

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lebedev.ri added a comment.

Could you please explain why there are both the knownbits-based checks, and checks for ISD::SIGN/ZERO_EXTEND nodes?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116039/new/

https://reviews.llvm.org/D116039

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