[llvm] de4e019 - [PowerPC] Add missed test case updates
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 21 12:55:27 PST 2021
Author: Nemanja Ivanovic
Date: 2021-12-21T14:55:19-06:00
New Revision: de4e0195ae1c39f1c3b07834b8e32c113f4f20eb
URL: https://github.com/llvm/llvm-project/commit/de4e0195ae1c39f1c3b07834b8e32c113f4f20eb
DIFF: https://github.com/llvm/llvm-project/commit/de4e0195ae1c39f1c3b07834b8e32c113f4f20eb.diff
LOG: [PowerPC] Add missed test case updates
In commit 1674d9b6b2da914619c7c197336bb74f7988cf38,
I missed adding the updates to existing test cases.
This should bring the bots back to green.
Added:
Modified:
llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
llvm/test/CodeGen/PowerPC/vsx.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll b/llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
index 727c2d328406..3a7bfcfb19f1 100644
--- a/llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
@@ -10,11 +10,21 @@ define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
; CHECK-LABEL: v2si64_cmp:
; CHECK: # %bb.0:
; CHECK-NEXT: vcmpequw 2, 2, 3
+; CHECK-NEXT: addis 3, 2, .LCPI0_0 at toc@ha
+; CHECK-NEXT: addi 3, 3, .LCPI0_0 at toc@l
+; CHECK-NEXT: lvx 3, 0, 3
+; CHECK-NEXT: vperm 3, 2, 2, 3
+; CHECK-NEXT: xxland 34, 35, 34
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: v2si64_cmp:
; CHECK-BE: # %bb.0:
; CHECK-BE-NEXT: vcmpequw 2, 2, 3
+; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0 at toc@ha
+; CHECK-BE-NEXT: addi 3, 3, .LCPI0_0 at toc@l
+; CHECK-BE-NEXT: lxvw4x 35, 0, 3
+; CHECK-BE-NEXT: vperm 3, 2, 2, 3
+; CHECK-BE-NEXT: xxland 34, 35, 34
; CHECK-BE-NEXT: blr
%cmp = icmp eq <2 x i64> %x, %y
%result = sext <2 x i1> %cmp to <2 x i64>
diff --git a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
index 0bcf03450b5d..eee3ff42bd13 100644
--- a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
@@ -11979,9 +11979,14 @@ define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) {
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI100_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI100_0 at toc@l
; PWR7-NEXT: xxland 34, 34, 0
; PWR7-NEXT: vcmpequw 2, 2, 3
+; PWR7-NEXT: lxvw4x 35, 0, 3
; PWR7-NEXT: xxlnor 34, 34, 34
+; PWR7-NEXT: vperm 3, 2, 2, 3
+; PWR7-NEXT: xxland 34, 35, 34
; PWR7-NEXT: blr
;
; PWR8-LABEL: ugt_1_v2i64:
@@ -12045,8 +12050,13 @@ define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
; PWR7-NEXT: lxvw4x 0, 0, 3
+; PWR7-NEXT: addis 3, 2, .LCPI101_0 at toc@ha
+; PWR7-NEXT: addi 3, 3, .LCPI101_0 at toc@l
; PWR7-NEXT: xxland 34, 34, 0
; PWR7-NEXT: vcmpequw 2, 2, 3
+; PWR7-NEXT: lxvw4x 35, 0, 3
+; PWR7-NEXT: vperm 3, 2, 2, 3
+; PWR7-NEXT: xxland 34, 35, 34
; PWR7-NEXT: blr
;
; PWR8-LABEL: ult_2_v2i64:
diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll
index a62f006eaeb1..d882050b2e5a 100644
--- a/llvm/test/CodeGen/PowerPC/vsx.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx.ll
@@ -2032,16 +2032,31 @@ define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test65:
; CHECK: # %bb.0:
; CHECK-NEXT: vcmpequw v2, v2, v3
+; CHECK-NEXT: addis r3, r2, .LCPI59_0 at toc@ha
+; CHECK-NEXT: addi r3, r3, .LCPI59_0 at toc@l
+; CHECK-NEXT: lxvw4x v3, 0, r3
+; CHECK-NEXT: vperm v3, v2, v2, v3
+; CHECK-NEXT: xxland v2, v3, v2
; CHECK-NEXT: blr
;
; CHECK-REG-LABEL: test65:
; CHECK-REG: # %bb.0:
; CHECK-REG-NEXT: vcmpequw v2, v2, v3
+; CHECK-REG-NEXT: addis r3, r2, .LCPI59_0 at toc@ha
+; CHECK-REG-NEXT: addi r3, r3, .LCPI59_0 at toc@l
+; CHECK-REG-NEXT: lxvw4x v3, 0, r3
+; CHECK-REG-NEXT: vperm v3, v2, v2, v3
+; CHECK-REG-NEXT: xxland v2, v3, v2
; CHECK-REG-NEXT: blr
;
; CHECK-FISL-LABEL: test65:
; CHECK-FISL: # %bb.0:
-; CHECK-FISL-NEXT: vcmpequw v2, v2, v3
+; CHECK-FISL-NEXT: vcmpequw v3, v2, v3
+; CHECK-FISL-NEXT: addis r3, r2, .LCPI59_0 at toc@ha
+; CHECK-FISL-NEXT: addi r3, r3, .LCPI59_0 at toc@l
+; CHECK-FISL-NEXT: lxvw4x v2, 0, r3
+; CHECK-FISL-NEXT: vperm v2, v3, v3, v2
+; CHECK-FISL-NEXT: xxland v2, v2, v3
; CHECK-FISL-NEXT: blr
;
; CHECK-LE-LABEL: test65:
@@ -2059,19 +2074,34 @@ define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test66:
; CHECK: # %bb.0:
; CHECK-NEXT: vcmpequw v2, v2, v3
+; CHECK-NEXT: addis r3, r2, .LCPI60_0 at toc@ha
+; CHECK-NEXT: addi r3, r3, .LCPI60_0 at toc@l
+; CHECK-NEXT: lxvw4x v3, 0, r3
; CHECK-NEXT: xxlnor v2, v2, v2
+; CHECK-NEXT: vperm v3, v2, v2, v3
+; CHECK-NEXT: xxland v2, v3, v2
; CHECK-NEXT: blr
;
; CHECK-REG-LABEL: test66:
; CHECK-REG: # %bb.0:
; CHECK-REG-NEXT: vcmpequw v2, v2, v3
+; CHECK-REG-NEXT: addis r3, r2, .LCPI60_0 at toc@ha
+; CHECK-REG-NEXT: addi r3, r3, .LCPI60_0 at toc@l
+; CHECK-REG-NEXT: lxvw4x v3, 0, r3
; CHECK-REG-NEXT: xxlnor v2, v2, v2
+; CHECK-REG-NEXT: vperm v3, v2, v2, v3
+; CHECK-REG-NEXT: xxland v2, v3, v2
; CHECK-REG-NEXT: blr
;
; CHECK-FISL-LABEL: test66:
; CHECK-FISL: # %bb.0:
; CHECK-FISL-NEXT: vcmpequw v2, v2, v3
-; CHECK-FISL-NEXT: xxlnor v2, v2, v2
+; CHECK-FISL-NEXT: xxlnor v3, v2, v2
+; CHECK-FISL-NEXT: addis r3, r2, .LCPI60_0 at toc@ha
+; CHECK-FISL-NEXT: addi r3, r3, .LCPI60_0 at toc@l
+; CHECK-FISL-NEXT: lxvw4x v2, 0, r3
+; CHECK-FISL-NEXT: vperm v2, v3, v3, v2
+; CHECK-FISL-NEXT: xxland v2, v2, v3
; CHECK-FISL-NEXT: blr
;
; CHECK-LE-LABEL: test66:
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