[PATCH] D114198: [GlobalISel] Rework more/fewer elements for vectors

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:3698
+                           MachineOperand &Op) {
+  assert((Op.isReg() || Op.isImm() || Op.isPredicate()) && "Unsupported type");
+  for (unsigned i = 0; i < N; ++i) {
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Convert if chain to else if and use llvm_unreachable instead of having to keep this list consistent


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:3743
+  // Split vector input operands into NumElts sub-vectors + Leftover. Other
+  // operands (listed in NonVecOpIndices) will be used as is witout splitting;
+  // examples: compare predicate in icmp and fcmp (op 1), vector select with i1
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Typo witout


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Comment at: llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp:231
+  auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
+  SmallVector<Register, 4> Regs;
+  for (auto Op : Unmerge.getInstr()->defs())
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arsenm wrote:
> 4 seems too small, use the default or 8?
Same applies elsewhere in patch


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114198/new/

https://reviews.llvm.org/D114198