[PATCH] D116039: [X86] Combine reduce (add (mul x, y)) to VNNI instruction.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke marked an inline comment as done.
LuoYuanke added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:41756-41774
+// (mul (zext a), (sext, b))
+static bool detectExtMul(const SDValue &Mul, SDValue &Op0, SDValue &Op1) {
+  Op0 = Mul.getOperand(0);
+  Op1 = Mul.getOperand(1);
+
+  // The operand1 should be signed extend
+  if (Op0.getOpcode() == ISD::SIGN_EXTEND)
----------------
craig.topper wrote:
> lebedev.ri wrote:
> > Any explicit checks for extension/truncation and their bitwidth delta instantly make me suspicious nowadays.
> > Does this deal with commutativity?
> > I think what you want to check is the number of known sign bits / known leading zero bits.
> If the sign extend side can be proven to be positive, the sign extend might be hidden as zero extend. This is why tryMAddReplacement checks for FreeTruncations and calls ComputeNumSignBits.
Thanks Craig and Roman. I enhanced it in the new patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116039/new/

https://reviews.llvm.org/D116039