[PATCH] D115862: [LoongArch][test] (5/5) Add encoding and mnemonics tests

[WÁNG Xuěruì via Phabricator via llvm-commits]

xen0n added a comment.

In D115862#3204232 <https://reviews.llvm.org/D115862#3204232>, @SixWeining wrote:

> Different compiler communities use different names. This is the reality not only for LoongArch but also other targets.
> Yes, I agree with you that binutils, llvm, qemu using same names is good for maintenace although this has not been achieved by other targets (like RISCV).

Yeah maybe others didn't do this, but we're a new target, so we might as well do better. In the end we could even figure out the best practice for others to possibly follow, so I still think such an approach is feasible.

Also note that RISC-V actually has the centralized riscv-opcodes <https://github.com/riscv/riscv-opcodes> project for instruction encodings; and their insn format names are sane, unlike LoongArch, so in fact the RISC-V ports from different projects still can standardize naming.

> So, are you happy with the names defined for LoongArch in binutils?
>
> In binutils-gdb/opcodes/loongarch-opc.c
>
>   { 0x00c00000, 0xffc00000, "bstrpick.d",   "r0:5,r5:5,u16:6,u10:6",    0,          0,  0,  0 },
>
> We may consider using `R0_5_R5_5_U16_6_U10_6` as the instruction format name for the `bstrpick.d` instruction.

This is even worse than ad-hoc `BSTR_D` names, because the name becomes too long and unwieldy to pronounce and use. (With names like `DJUk6Um6` or `FdFjFkCa` you can at least spell every letter out individually.) And a lot of details are redundant, like the "r" prefix implying the slot is 5-bit wide, and so on.


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