[llvm] de90490 - Revert "[ARM] Use range-based for loops (NFC)"
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 20 10:51:42 PST 2021
Author: Kazu Hirata
Date: 2021-12-20T10:51:36-08:00
New Revision: de904900600f11a65cdf44023061600b668e9df5
URL: https://github.com/llvm/llvm-project/commit/de904900600f11a65cdf44023061600b668e9df5
DIFF: https://github.com/llvm/llvm-project/commit/de904900600f11a65cdf44023061600b668e9df5.diff
LOG: Revert "[ARM] Use range-based for loops (NFC)"
This reverts commit 93d79cac2ede436e1e3e91b5aff702914cdfbca7.
This patch seems to break
llvm/test/CodeGen/ARM/constant-islands-cfg.mir under asan.
Added:
Modified:
llvm/lib/Target/ARM/A15SDOptimizer.cpp
llvm/lib/Target/ARM/ARMCallingConv.cpp
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/A15SDOptimizer.cpp b/llvm/lib/Target/ARM/A15SDOptimizer.cpp
index d0efecad63bc5..f4d0f4a6d6b00 100644
--- a/llvm/lib/Target/ARM/A15SDOptimizer.cpp
+++ b/llvm/lib/Target/ARM/A15SDOptimizer.cpp
@@ -592,15 +592,16 @@ bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
bool Modified = false;
- for (unsigned I : Defs) {
+ for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
+ I != E; ++I) {
// Follow the def-use chain for this DPR through COPYs, and also through
// PHIs (which are essentially multi-way COPYs). It is because of PHIs that
// we can end up with multiple defs of this DPR.
SmallVector<MachineInstr *, 8> DefSrcs;
- if (!Register::isVirtualRegister(I))
+ if (!Register::isVirtualRegister(*I))
continue;
- MachineInstr *Def = MRI->getVRegDef(I);
+ MachineInstr *Def = MRI->getVRegDef(*I);
if (!Def)
continue;
@@ -627,17 +628,18 @@ bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
if (NewReg != 0) {
Modified = true;
- for (MachineOperand *Use : Uses) {
+ for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
+ E = Uses.end(); I != E; ++I) {
// Make sure to constrain the register class of the new register to
// match what we're replacing. Otherwise we can optimize a DPR_VFP2
// reference into a plain DPR, and that will end poorly. NewReg is
// always virtual here, so there will always be a matching subclass
// to find.
- MRI->constrainRegClass(NewReg, MRI->getRegClass(Use->getReg()));
+ MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
- LLVM_DEBUG(dbgs() << "Replacing operand " << *Use << " with "
+ LLVM_DEBUG(dbgs() << "Replacing operand " << **I << " with "
<< printReg(NewReg) << "\n");
- Use->substVirtReg(NewReg, 0, *TRI);
+ (*I)->substVirtReg(NewReg, 0, *TRI);
}
}
Replacements[MI] = NewReg;
diff --git a/llvm/lib/Target/ARM/ARMCallingConv.cpp b/llvm/lib/Target/ARM/ARMCallingConv.cpp
index 32f3a4a632f5e..d8d9ca3b912fa 100644
--- a/llvm/lib/Target/ARM/ARMCallingConv.cpp
+++ b/llvm/lib/Target/ARM/ARMCallingConv.cpp
@@ -230,9 +230,10 @@ static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned ValNo, MVT ValVT,
unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
if (RegResult) {
- for (CCValAssign &PendingMember : PendingMembers) {
- PendingMember.convertToReg(RegResult);
- State.addLoc(PendingMember);
+ for (SmallVectorImpl<CCValAssign>::iterator It = PendingMembers.begin();
+ It != PendingMembers.end(); ++It) {
+ It->convertToReg(RegResult);
+ State.addLoc(*It);
++RegResult;
}
PendingMembers.clear();
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 20b6796bc3345..c2ca4708c208a 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -310,7 +310,8 @@ void ARMConstantIslands::verify() {
BBInfo[RHS.getNumber()].postOffset();
}));
LLVM_DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n");
- for (CPUser &U : CPUsers) {
+ for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
+ CPUser &U = CPUsers[i];
unsigned UserOffset = getUserOffset(U);
// Verify offset using the real max displacement without the safety
// adjustment.
@@ -480,8 +481,8 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
bool BRChange = false;
- for (auto &IB : ImmBranches)
- BRChange |= fixupImmediateBr(IB);
+ for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
+ BRChange |= fixupImmediateBr(ImmBranches[i]);
if (BRChange && ++NoBRIters > 30)
report_fatal_error("Branch Fix Up pass failed to converge!");
LLVM_DEBUG(dumpBBs());
@@ -696,9 +697,10 @@ ARMConstantIslands::findConstPoolEntry(unsigned CPI,
std::vector<CPEntry> &CPEs = CPEntries[CPI];
// Number of entries per constpool index should be small, just do a
// linear search.
- for (CPEntry &CPE : CPEs)
- if (CPE.CPEMI == CPEMI)
- return &CPE;
+ for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
+ if (CPEs[i].CPEMI == CPEMI)
+ return &CPEs[i];
+ }
return nullptr;
}
@@ -1232,27 +1234,27 @@ int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) {
// No. Look for previously created clones of the CPE that are in range.
unsigned CPI = getCombinedIndex(CPEMI);
std::vector<CPEntry> &CPEs = CPEntries[CPI];
- for (CPEntry &CPE : CPEs) {
+ for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
// We already tried this one
- if (CPE.CPEMI == CPEMI)
+ if (CPEs[i].CPEMI == CPEMI)
continue;
// Removing CPEs can leave empty entries, skip
- if (CPE.CPEMI == nullptr)
+ if (CPEs[i].CPEMI == nullptr)
continue;
- if (isCPEntryInRange(UserMI, UserOffset, CPE.CPEMI, U.getMaxDisp(),
- U.NegOk)) {
- LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#" << CPE.CPI
- << "\n");
+ if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getMaxDisp(),
+ U.NegOk)) {
+ LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#"
+ << CPEs[i].CPI << "\n");
// Point the CPUser node to the replacement
- U.CPEMI = CPE.CPEMI;
+ U.CPEMI = CPEs[i].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
for (MachineOperand &MO : UserMI->operands())
if (MO.isCPI()) {
- MO.setIndex(CPE.CPI);
+ MO.setIndex(CPEs[i].CPI);
break;
}
// Adjust the refcount of the clone...
- CPE.RefCount++;
+ CPEs[i].RefCount++;
// ...and the original. If we didn't remove the old entry, none of the
// addresses changed, so we don't need another pass.
return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1;
@@ -1673,14 +1675,15 @@ void ARMConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
/// are zero.
bool ARMConstantIslands::removeUnusedCPEntries() {
unsigned MadeChange = false;
- for (std::vector<CPEntry> &CPEs : CPEntries) {
- for (CPEntry &CPE : CPEs) {
- if (CPE.RefCount == 0 && CPE.CPEMI) {
- removeDeadCPEMI(CPE.CPEMI);
- CPE.CPEMI = nullptr;
- MadeChange = true;
+ for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
+ std::vector<CPEntry> &CPEs = CPEntries[i];
+ for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
+ if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
+ removeDeadCPEMI(CPEs[j].CPEMI);
+ CPEs[j].CPEMI = nullptr;
+ MadeChange = true;
+ }
}
- }
}
return MadeChange;
}
@@ -1826,7 +1829,8 @@ bool ARMConstantIslands::optimizeThumb2Instructions() {
bool MadeChange = false;
// Shrink ADR and LDR from constantpool.
- for (CPUser &U : CPUsers) {
+ for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
+ CPUser &U = CPUsers[i];
unsigned Opcode = U.MI->getOpcode();
unsigned NewOpc = 0;
unsigned Scale = 1;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 3d45db3496447..e38938e9e5982 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8400,8 +8400,9 @@ static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
SDLoc DL(Op);
SmallVector<SDValue, 8> VTBLMask;
- for (int I : ShuffleMask)
- VTBLMask.push_back(DAG.getConstant(I, DL, MVT::i32));
+ for (ArrayRef<int>::iterator
+ I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
+ VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32));
if (V2.getNode()->isUndef())
return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
@@ -10681,23 +10682,25 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
// associated with.
DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2>> CallSiteNumToLPad;
unsigned MaxCSNum = 0;
- for (MachineBasicBlock &BB : *MF) {
- if (!BB.isEHPad())
- continue;
+ for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
+ ++BB) {
+ if (!BB->isEHPad()) continue;
// FIXME: We should assert that the EH_LABEL is the first MI in the landing
// pad.
- for (MachineInstr &II : BB) {
- if (!II.isEHLabel())
- continue;
+ for (MachineBasicBlock::iterator
+ II = BB->begin(), IE = BB->end(); II != IE; ++II) {
+ if (!II->isEHLabel()) continue;
- MCSymbol *Sym = II.getOperand(0).getMCSymbol();
+ MCSymbol *Sym = II->getOperand(0).getMCSymbol();
if (!MF->hasCallSiteLandingPad(Sym)) continue;
SmallVectorImpl<unsigned> &CallSiteIdxs = MF->getCallSiteLandingPad(Sym);
- for (unsigned Idx : CallSiteIdxs) {
- CallSiteNumToLPad[Idx].push_back(&BB);
- MaxCSNum = std::max(MaxCSNum, Idx);
+ for (SmallVectorImpl<unsigned>::iterator
+ CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
+ CSI != CSE; ++CSI) {
+ CallSiteNumToLPad[*CSI].push_back(&*BB);
+ MaxCSNum = std::max(MaxCSNum, *CSI);
}
break;
}
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index f822672c4477d..766a45cd4a951 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -1328,8 +1328,8 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
bool Changed = false;
// Process inner loops first.
- for (MachineLoop *L : *ML)
- Changed |= ProcessLoop(L);
+ for (auto I = ML->begin(), E = ML->end(); I != E; ++I)
+ Changed |= ProcessLoop(*I);
LLVM_DEBUG({
dbgs() << "ARM Loops: Processing loop containing:\n";
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index bfe078b068614..73e792e98b450 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -137,18 +137,21 @@ class UnwindContext {
int getFPReg() const { return FPReg; }
void emitFnStartLocNotes() const {
- for (const SMLoc &Loc : FnStartLocs)
- Parser.Note(Loc, ".fnstart was specified here");
+ for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
+ FI != FE; ++FI)
+ Parser.Note(*FI, ".fnstart was specified here");
}
void emitCantUnwindLocNotes() const {
- for (const SMLoc &Loc : CantUnwindLocs)
- Parser.Note(Loc, ".cantunwind was specified here");
+ for (Locs::const_iterator UI = CantUnwindLocs.begin(),
+ UE = CantUnwindLocs.end(); UI != UE; ++UI)
+ Parser.Note(*UI, ".cantunwind was specified here");
}
void emitHandlerDataLocNotes() const {
- for (const SMLoc &Loc : HandlerDataLocs)
- Parser.Note(Loc, ".handlerdata was specified here");
+ for (Locs::const_iterator HI = HandlerDataLocs.begin(),
+ HE = HandlerDataLocs.end(); HI != HE; ++HI)
+ Parser.Note(*HI, ".handlerdata was specified here");
}
void emitPersonalityLocNotes() const {
@@ -2570,15 +2573,17 @@ class ARMOperand : public MCParsedAsmOperand {
void addRegListOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const SmallVectorImpl<unsigned> &RegList = getRegList();
- for (unsigned Reg : RegList)
- Inst.addOperand(MCOperand::createReg(Reg));
+ for (SmallVectorImpl<unsigned>::const_iterator
+ I = RegList.begin(), E = RegList.end(); I != E; ++I)
+ Inst.addOperand(MCOperand::createReg(*I));
}
void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const SmallVectorImpl<unsigned> &RegList = getRegList();
- for (unsigned Reg : RegList)
- Inst.addOperand(MCOperand::createReg(Reg));
+ for (SmallVectorImpl<unsigned>::const_iterator
+ I = RegList.begin(), E = RegList.end(); I != E; ++I)
+ Inst.addOperand(MCOperand::createReg(*I));
}
void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
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