[PATCH] D113376: [AArch64][SVE] Lower shuffles to permute instructions: zip1/2, uzp1/2, trn1/2

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll:419
+
+define void @zip2_v32i8(<32 x i8>* %a, <32 x i8>* %b) #1 {
+; CHECK-LABEL: zip2_v32i8:
----------------
I think there's value in adding a comment that states why we can safely emit zip2 instructions.  Not too detailed, it's just worth drawing the readers attention to the fact that for this and related tests the runtime vector length is known.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll:481
+
+define void @uzp_v32i8(<32 x i8>* %a, <32 x i8>* %b) #1 {
+; CHECK-LABEL: uzp_v32i8:
----------------
As above, there's value in adding a comment that mentions why we can safely emit uzp instructions.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll:627
+
+define void @zip_vscale2_4(<4 x double>* %a, <4 x double>* %b) #2 {
+; CHECK-LABEL: zip_vscale2_4:
----------------
Please add a small comment to highlight this is a negative test and why only zip1 instructions are emitted.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113376/new/

https://reviews.llvm.org/D113376