[llvm] eb66f06 - Revert "[DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience"

[Shivam Gupta via llvm-commits]

Author: Shivam Gupta
Date: 2021-12-20T21:43:40+05:30
New Revision: eb66f0662ad9dd78166ee912611308d301f513a2

URL: https://github.com/llvm/llvm-project/commit/eb66f0662ad9dd78166ee912611308d301f513a2
DIFF: https://github.com/llvm/llvm-project/commit/eb66f0662ad9dd78166ee912611308d301f513a2.diff

LOG: Revert "[DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience"

This reverts commit 731bde1ed30fcd8474ea6b88c3a9fc3072d2dca4.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    llvm/test/CodeGen/RISCV/optnone-store-no-combine.ll


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 067ad819e0d26..8055eb9a82d64 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -18395,8 +18395,8 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
   if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
     if (ST->isUnindexed() && ST->isSimple() &&
         ST1->isUnindexed() && ST1->isSimple()) {
-      if (OptLevel != CodeGenOpt::None && ST1->getBasePtr() == Ptr &&
-          ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() &&
+      if (ST1->getBasePtr() == Ptr && ST1->getValue() == Value &&
+          ST->getMemoryVT() == ST1->getMemoryVT() &&
           ST->getAddressSpace() == ST1->getAddressSpace()) {
         // If this is a store followed by a store with the same value to the
         // same location, then the store is dead/noop.

diff  --git a/llvm/test/CodeGen/RISCV/optnone-store-no-combine.ll b/llvm/test/CodeGen/RISCV/optnone-store-no-combine.ll
deleted file mode 100644
index 9648fdbfd0b04..0000000000000
--- a/llvm/test/CodeGen/RISCV/optnone-store-no-combine.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
-
-; This test case makes sure that the same store will not get optimize out by DAGCombiner
-; and verify that codegen has those stores in it. It will help to improve debug experience.
-
-define dso_local void @foo(i32* %p) noinline nounwind optnone {
-; CHECK-LABEL: foo:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    li a1, 8
-; CHECK-NEXT:    sw a1, 0(a0)
-; CHECK-NEXT:    sw a1, 0(a0)
-; CHECK-NEXT:    ret
-  store i32 8, i32* %p, align 4
-  store i32 8, i32* %p, align 4
-  ret void
-}