[PATCH] D116044: [AMDGPU] Enable devergence predicates for ctlz/cttz

[Alexander via Phabricator via llvm-commits]

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ctlz/cttz get lowered to the set of target opcodes

  This change enables the ISel to select SALU or VALU form acording to the SDNode divergence.
  CTLZ - S_FLBIT_I32_B32 if uniform and V_FFBH_U32_e64 if divergent
  CTTZ - S_FF1_I32_B32   if uniform and V_FFBL_B32_e64 if divergent
  Also @llvm.amdgcn.sffbh.i32 gets lowered to S_FLBIT_I32 if uniform and V_FFBH_I32_e64 if divergent
  NOTE: 64bit versions S_FF1_I32_B64 and S_FLBIT_I32_B64 are not currently supported by the DAG ISel
  ctlz/cttz with i64 input get splitted to two 32bit instructions. Newertheless, they already have the patterns
  and were equipped with the divergence predicates to make sure they will be selected correctly when enabled.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116044

Files:
  llvm/lib/Target/AMDGPU/SOPInstructions.td
  llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll

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