[PATCH] D115922: [RISCV] Override hasAndNotCompare to use more andn when have Zbb extension.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan updated this revision to Diff 395412.
jacquesguan added a comment.

rebase to pre-commit test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115922/new/

https://reviews.llvm.org/D115922

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll


Index: llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
+++ llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
@@ -641,10 +641,8 @@
 ;
 ; RV64ZBB-LABEL: andn_seqz_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    sext.w a2, a1
-; RV64ZBB-NEXT:    and a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    sext.w a0, a0
-; RV64ZBB-NEXT:    xor a0, a0, a2
 ; RV64ZBB-NEXT:    seqz a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
@@ -671,8 +669,7 @@
 ;
 ; RV64ZBB-LABEL: andn_seqz_i64:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    and a0, a0, a1
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    seqz a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
@@ -699,10 +696,8 @@
 ;
 ; RV64ZBB-LABEL: andn_snez_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    sext.w a2, a1
-; RV64ZBB-NEXT:    and a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    sext.w a0, a0
-; RV64ZBB-NEXT:    xor a0, a0, a2
 ; RV64ZBB-NEXT:    snez a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
@@ -729,8 +724,7 @@
 ;
 ; RV64ZBB-LABEL: andn_snez_i64:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    and a0, a0, a1
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    snez a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
Index: llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
+++ llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
@@ -568,8 +568,7 @@
 ;
 ; RV32ZBB-LABEL: andn_seqz_i32:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    and a0, a0, a1
-; RV32ZBB-NEXT:    xor a0, a0, a1
+; RV32ZBB-NEXT:    andn a0, a1, a0
 ; RV32ZBB-NEXT:    seqz a0, a0
 ; RV32ZBB-NEXT:    ret
 ;
@@ -625,8 +624,7 @@
 ;
 ; RV32ZBB-LABEL: andn_snez_i32:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    and a0, a0, a1
-; RV32ZBB-NEXT:    xor a0, a0, a1
+; RV32ZBB-NEXT:    andn a0, a1, a0
 ; RV32ZBB-NEXT:    snez a0, a0
 ; RV32ZBB-NEXT:    ret
 ;
Index: llvm/lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -315,7 +315,7 @@
   bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
   bool isCheapToSpeculateCttz() const override;
   bool isCheapToSpeculateCtlz() const override;
-  bool hasAndNot(SDValue Y) const override;
+  bool hasAndNotCompare(SDValue Y) const override;
   bool shouldSinkOperands(Instruction *I,
                           SmallVectorImpl<Use *> &Ops) const override;
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1166,7 +1166,7 @@
   return Subtarget.hasStdExtZbb();
 }
 
-bool RISCVTargetLowering::hasAndNot(SDValue Y) const {
+bool RISCVTargetLowering::hasAndNotCompare(SDValue Y) const {
   EVT VT = Y.getValueType();
 
   // FIXME: Support vectors once we have tests.


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