[PATCH] D106237: [ISel] Port AArch64 HADD and RHADD to ISel
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 19 13:20:07 PST 2021
dmgreen updated this revision to Diff 395353.
dmgreen edited the summary of this revision.
dmgreen added a comment.
Herald added subscribers: ecnelises, kerbowa, pengfei, nhaehnle, jvesely.
This now:
- Calls the nodes AVGFLOOR and AVGCEIL.
- Ports X86ISD::AVG to use AVGCEILU.
- Doesn't remove detectAVGPattern, as it can detect more pattern, such as illegal types. It adds some basic widening support to handle them.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106237/new/
https://reviews.llvm.org/D106237
Files:
llvm/include/llvm/CodeGen/ISDOpcodes.h
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/include/llvm/Target/TargetSelectionDAG.td
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/lib/Target/X86/X86InstrSSE.td
llvm/lib/Target/X86/X86IntrinsicsInfo.h
llvm/test/CodeGen/AArch64/arm64-vhadd.ll
llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
llvm/test/CodeGen/X86/avg.ll
llvm/test/CodeGen/X86/min-legal-vector-width.ll
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