[PATCH] D115975: [RISCV] Disable interleaving scalar loops in the loop vectorizer.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 17 15:06:16 PST 2021
craig.topper created this revision.
craig.topper added reviewers: asb, luismarques, frasercrmck, jrtc27.
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The loop vectorize can interleave scalar loops even if it doesn't
vectorize them. I don't believe we inteded to enable this when
we enabled interleaving for vector instructions.
Disable interleaving for VF=1 like X86 and AMDGPU already do. Test
lifted from AMDGPU.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D115975
Files:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
llvm/test/Transforms/LoopVectorize/RISCV/unroll-in-loop-vectorizer.ll
Index: llvm/test/Transforms/LoopVectorize/RISCV/unroll-in-loop-vectorizer.ll
===================================================================
--- /dev/null
+++ llvm/test/Transforms/LoopVectorize/RISCV/unroll-in-loop-vectorizer.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -mtriple=riscv64 -mattr=+experimental-v -loop-vectorize < %s | FileCheck %s
+
+; Make sure we don't unroll scalar loops in the loop vectorizer.
+;
+define void @small_loop(i32* nocapture %inArray, i32 %size) nounwind {
+; CHECK-LABEL: @small_loop(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i32 [[SIZE:%.*]], 0
+; CHECK-NEXT: br i1 [[TMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
+; CHECK: loop.preheader:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV1:%.*]], [[LOOP]] ], [ 0, [[LOOP_PREHEADER]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[INARRAY:%.*]], i32 [[IV]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = add nsw i32 [[TMP2]], 6
+; CHECK-NEXT: store i32 [[TMP3]], i32* [[TMP1]], align 4
+; CHECK-NEXT: [[IV1]] = add i32 [[IV]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV1]], [[SIZE]]
+; CHECK-NEXT: br i1 [[COND]], label [[EXIT_LOOPEXIT:%.*]], label [[LOOP]]
+; CHECK: exit.loopexit:
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: ret void
+;
+entry:
+ %0 = icmp sgt i32 %size, 0
+ br i1 %0, label %loop, label %exit
+
+loop: ; preds = %entry, %loop
+ %iv = phi i32 [ %iv1, %loop ], [ 0, %entry ]
+ %1 = getelementptr inbounds i32, i32* %inArray, i32 %iv
+ %2 = load i32, i32* %1, align 4
+ %3 = add nsw i32 %2, 6
+ store i32 %3, i32* %1, align 4
+ %iv1 = add i32 %iv, 1
+; %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+ %cond = icmp eq i32 %iv1, %size
+ br i1 %cond, label %exit, label %loop
+
+exit: ; preds = %loop, %entry
+ ret void
+}
Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -178,7 +178,9 @@
}
unsigned getMaxInterleaveFactor(unsigned VF) {
- return ST->getMaxInterleaveFactor();
+ // If the loop will not be vectorized, don't interleave the loop.
+ // Let regular unroll to unroll the loop.
+ return VF == 1 ? 1 : ST->getMaxInterleaveFactor();
}
};
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