[llvm] be41996 - [RISCV} Add FSGNJ_H to isAsCheapAsAMove and isCopyInstrImpl.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-12-17T09:14:20-08:00
New Revision: be41996f4f8cdaa4eb36c264183e508c1bd0455e

URL: https://github.com/llvm/llvm-project/commit/be41996f4f8cdaa4eb36c264183e508c1bd0455e
DIFF: https://github.com/llvm/llvm-project/commit/be41996f4f8cdaa4eb36c264183e508c1bd0455e.diff

LOG: [RISCV} Add FSGNJ_H to isAsCheapAsAMove and isCopyInstrImpl.

This matches FSGNJ_S and FSGNJ_D.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 132a5291715c0..2e2e00886d57a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1060,6 +1060,7 @@ bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
     break;
   case RISCV::FSGNJ_D:
   case RISCV::FSGNJ_S:
+  case RISCV::FSGNJ_H:
     // The canonical floating-point move is fsgnj rd, rs, rs.
     return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
            MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
@@ -1088,6 +1089,7 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
     break;
   case RISCV::FSGNJ_D:
   case RISCV::FSGNJ_S:
+  case RISCV::FSGNJ_H:
     // The canonical floating-point move is fsgnj rd, rs, rs.
     if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
         MI.getOperand(1).getReg() == MI.getOperand(2).getReg())