[PATCH] D115945: [AMDGPU][GlobalISel] Eliminate cross regbank copies of constants

[Mirko Brkusanin via Phabricator via llvm-commits]

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Consider uses when selecting regbank for G_CONSTANT:
By default we assign SGPR because we do not know what the uses will be at the
time of selecting. If it turns out we need it as a VGPR then a repairing is done
by inserting a copy, same as for any other instruction.

For constants with multiple uses we add a new regbank combiner. If all uses are
the same non SGPR bank (will be copies to that new bank inserted by the
RegBankSelect), we change original constant to new bank, remove copies and
update uses.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115945

Files:
  llvm/lib/Target/AMDGPU/AMDGPUCombine.td
  llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
  llvm/test/CodeGen/AMDGPU/ctlz.ll
  llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
  llvm/test/CodeGen/AMDGPU/cttz.ll
  llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll