[llvm] 29607b3 - [x86] add RUN line to test file for 32-bit target; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 17 07:51:11 PST 2021
Author: Sanjay Patel
Date: 2021-12-17T10:51:02-05:00
New Revision: 29607b3400721aa264cd73749925e15959f4b69b
URL: https://github.com/llvm/llvm-project/commit/29607b3400721aa264cd73749925e15959f4b69b
DIFF: https://github.com/llvm/llvm-project/commit/29607b3400721aa264cd73749925e15959f4b69b.diff
LOG: [x86] add RUN line to test file for 32-bit target; NFC
More coverage for D115885
Added:
Modified:
llvm/test/CodeGen/X86/ftrunc.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/ftrunc.ll b/llvm/test/CodeGen/X86/ftrunc.ll
index 14191f140470c..eed888bd2e848 100644
--- a/llvm/test/CodeGen/X86/ftrunc.ll
+++ b/llvm/test/CodeGen/X86/ftrunc.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX1
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=X64_AVX1
+; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefixes=X32_AVX1
define float @trunc_unsigned_f32(float %x) #0 {
; SSE2-LABEL: trunc_unsigned_f32:
@@ -17,10 +18,20 @@ define float @trunc_unsigned_f32(float %x) #0 {
; SSE41-NEXT: roundss $11, %xmm0, %xmm0
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_unsigned_f32:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_unsigned_f32:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_unsigned_f32:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %eax
+; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32_AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovss %xmm0, (%esp)
+; X32_AVX1-NEXT: flds (%esp)
+; X32_AVX1-NEXT: popl %eax
+; X32_AVX1-NEXT: retl
%i = fptoui float %x to i32
%r = uitofp i32 %i to float
ret float %r
@@ -49,10 +60,24 @@ define double @trunc_unsigned_f64(double %x) #0 {
; SSE41-NEXT: roundsd $11, %xmm0, %xmm0
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_unsigned_f64:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_unsigned_f64:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_unsigned_f64:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %ebp
+; X32_AVX1-NEXT: movl %esp, %ebp
+; X32_AVX1-NEXT: andl $-8, %esp
+; X32_AVX1-NEXT: subl $8, %esp
+; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovsd %xmm0, (%esp)
+; X32_AVX1-NEXT: fldl (%esp)
+; X32_AVX1-NEXT: movl %ebp, %esp
+; X32_AVX1-NEXT: popl %ebp
+; X32_AVX1-NEXT: retl
%i = fptoui double %x to i64
%r = uitofp i64 %i to double
ret double %r
@@ -82,10 +107,15 @@ define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) #0 {
; SSE41-NEXT: roundps $11, %xmm0, %xmm0
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_unsigned_v4f32:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundps $11, %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_unsigned_v4f32:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundps $11, %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_unsigned_v4f32:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: vroundps $11, %xmm0, %xmm0
+; X32_AVX1-NEXT: retl
%i = fptoui <4 x float> %x to <4 x i32>
%r = uitofp <4 x i32> %i to <4 x float>
ret <4 x float> %r
@@ -129,10 +159,15 @@ define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) #0 {
; SSE41-NEXT: roundpd $11, %xmm0, %xmm0
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_unsigned_v2f64:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundpd $11, %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_unsigned_v2f64:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_unsigned_v2f64:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0
+; X32_AVX1-NEXT: retl
%i = fptoui <2 x double> %x to <2 x i64>
%r = uitofp <2 x i64> %i to <2 x double>
ret <2 x double> %r
@@ -206,10 +241,15 @@ define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) #0 {
; SSE41-NEXT: roundpd $11, %xmm1, %xmm1
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_unsigned_v4f64:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundpd $11, %ymm0, %ymm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_unsigned_v4f64:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundpd $11, %ymm0, %ymm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_unsigned_v4f64:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: vroundpd $11, %ymm0, %ymm0
+; X32_AVX1-NEXT: retl
%i = fptoui <4 x double> %x to <4 x i64>
%r = uitofp <4 x i64> %i to <4 x double>
ret <4 x double> %r
@@ -222,11 +262,24 @@ define float @trunc_signed_f32_no_fast_math(float %x) {
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: trunc_signed_f32_no_fast_math:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
-; AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_signed_f32_no_fast_math:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
+; X64_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_signed_f32_no_fast_math:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %eax
+; X32_AVX1-NEXT: .cfi_def_cfa_offset 8
+; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
+; X32_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovss %xmm0, (%esp)
+; X32_AVX1-NEXT: flds (%esp)
+; X32_AVX1-NEXT: popl %eax
+; X32_AVX1-NEXT: .cfi_def_cfa_offset 4
+; X32_AVX1-NEXT: retl
%i = fptosi float %x to i32
%r = sitofp i32 %i to float
ret float %r
@@ -246,10 +299,20 @@ define float @trunc_signed_f32_nsz(float %x) #0 {
; SSE41-NEXT: roundss $11, %xmm0, %xmm0
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_signed_f32_nsz:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_signed_f32_nsz:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_signed_f32_nsz:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %eax
+; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32_AVX1-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovss %xmm0, (%esp)
+; X32_AVX1-NEXT: flds (%esp)
+; X32_AVX1-NEXT: popl %eax
+; X32_AVX1-NEXT: retl
%i = fptosi float %x to i32
%r = sitofp i32 %i to float
ret float %r
@@ -262,11 +325,30 @@ define double @trunc_signed32_f64_no_fast_math(double %x) {
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: trunc_signed32_f64_no_fast_math:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0
-; AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_signed32_f64_no_fast_math:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0
+; X64_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_signed32_f64_no_fast_math:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %ebp
+; X32_AVX1-NEXT: .cfi_def_cfa_offset 8
+; X32_AVX1-NEXT: .cfi_offset %ebp, -8
+; X32_AVX1-NEXT: movl %esp, %ebp
+; X32_AVX1-NEXT: .cfi_def_cfa_register %ebp
+; X32_AVX1-NEXT: andl $-8, %esp
+; X32_AVX1-NEXT: subl $8, %esp
+; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0
+; X32_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovlps %xmm0, (%esp)
+; X32_AVX1-NEXT: fldl (%esp)
+; X32_AVX1-NEXT: movl %ebp, %esp
+; X32_AVX1-NEXT: popl %ebp
+; X32_AVX1-NEXT: .cfi_def_cfa %esp, 4
+; X32_AVX1-NEXT: retl
%i = fptosi double %x to i32
%r = sitofp i32 %i to double
ret double %r
@@ -284,10 +366,24 @@ define double @trunc_signed32_f64_nsz(double %x) #0 {
; SSE41-NEXT: roundsd $11, %xmm0, %xmm0
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_signed32_f64_nsz:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_signed32_f64_nsz:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_signed32_f64_nsz:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %ebp
+; X32_AVX1-NEXT: movl %esp, %ebp
+; X32_AVX1-NEXT: andl $-8, %esp
+; X32_AVX1-NEXT: subl $8, %esp
+; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovsd %xmm0, (%esp)
+; X32_AVX1-NEXT: fldl (%esp)
+; X32_AVX1-NEXT: movl %ebp, %esp
+; X32_AVX1-NEXT: popl %ebp
+; X32_AVX1-NEXT: retl
%i = fptosi double %x to i32
%r = sitofp i32 %i to double
ret double %r
@@ -300,11 +396,30 @@ define double @trunc_f32_signed32_f64_no_fast_math(float %x) {
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: trunc_f32_signed32_f64_no_fast_math:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
-; AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_f32_signed32_f64_no_fast_math:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
+; X64_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_f32_signed32_f64_no_fast_math:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %ebp
+; X32_AVX1-NEXT: .cfi_def_cfa_offset 8
+; X32_AVX1-NEXT: .cfi_offset %ebp, -8
+; X32_AVX1-NEXT: movl %esp, %ebp
+; X32_AVX1-NEXT: .cfi_def_cfa_register %ebp
+; X32_AVX1-NEXT: andl $-8, %esp
+; X32_AVX1-NEXT: subl $8, %esp
+; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
+; X32_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovlps %xmm0, (%esp)
+; X32_AVX1-NEXT: fldl (%esp)
+; X32_AVX1-NEXT: movl %ebp, %esp
+; X32_AVX1-NEXT: popl %ebp
+; X32_AVX1-NEXT: .cfi_def_cfa %esp, 4
+; X32_AVX1-NEXT: retl
%i = fptosi float %x to i32
%r = sitofp i32 %i to double
ret double %r
@@ -317,11 +432,26 @@ define double @trunc_f32_signed32_f64_nsz(float %x) #0 {
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: trunc_f32_signed32_f64_nsz:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
-; AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_f32_signed32_f64_nsz:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
+; X64_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_f32_signed32_f64_nsz:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %ebp
+; X32_AVX1-NEXT: movl %esp, %ebp
+; X32_AVX1-NEXT: andl $-8, %esp
+; X32_AVX1-NEXT: subl $8, %esp
+; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32_AVX1-NEXT: vcvttps2dq %xmm0, %xmm0
+; X32_AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovlps %xmm0, (%esp)
+; X32_AVX1-NEXT: fldl (%esp)
+; X32_AVX1-NEXT: movl %ebp, %esp
+; X32_AVX1-NEXT: popl %ebp
+; X32_AVX1-NEXT: retl
%i = fptosi float %x to i32
%r = sitofp i32 %i to double
ret double %r
@@ -334,11 +464,24 @@ define float @trunc_f64_signed32_f32_no_fast_math(double %x) {
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: trunc_f64_signed32_f32_no_fast_math:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0
-; AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_f64_signed32_f32_no_fast_math:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0
+; X64_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_f64_signed32_f32_no_fast_math:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %eax
+; X32_AVX1-NEXT: .cfi_def_cfa_offset 8
+; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0
+; X32_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovss %xmm0, (%esp)
+; X32_AVX1-NEXT: flds (%esp)
+; X32_AVX1-NEXT: popl %eax
+; X32_AVX1-NEXT: .cfi_def_cfa_offset 4
+; X32_AVX1-NEXT: retl
%i = fptosi double %x to i32
%r = sitofp i32 %i to float
ret float %r
@@ -351,11 +494,22 @@ define float @trunc_f64_signed32_f32_nsz(double %x) #0 {
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: trunc_f64_signed32_f32_nsz:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0
-; AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_f64_signed32_f32_nsz:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0
+; X64_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_f64_signed32_f32_nsz:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %eax
+; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32_AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0
+; X32_AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovss %xmm0, (%esp)
+; X32_AVX1-NEXT: flds (%esp)
+; X32_AVX1-NEXT: popl %eax
+; X32_AVX1-NEXT: retl
%i = fptosi double %x to i32
%r = sitofp i32 %i to float
ret float %r
@@ -369,11 +523,34 @@ define double @trunc_signed_f64_no_fast_math(double %x) {
; SSE-NEXT: cvtsi2sd %rax, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: trunc_signed_f64_no_fast_math:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vcvttsd2si %xmm0, %rax
-; AVX1-NEXT: vcvtsi2sd %rax, %xmm1, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_signed_f64_no_fast_math:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vcvttsd2si %xmm0, %rax
+; X64_AVX1-NEXT: vcvtsi2sd %rax, %xmm1, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_signed_f64_no_fast_math:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %ebp
+; X32_AVX1-NEXT: .cfi_def_cfa_offset 8
+; X32_AVX1-NEXT: .cfi_offset %ebp, -8
+; X32_AVX1-NEXT: movl %esp, %ebp
+; X32_AVX1-NEXT: .cfi_def_cfa_register %ebp
+; X32_AVX1-NEXT: andl $-8, %esp
+; X32_AVX1-NEXT: subl $24, %esp
+; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32_AVX1-NEXT: vmovsd %xmm0, (%esp)
+; X32_AVX1-NEXT: fldl (%esp)
+; X32_AVX1-NEXT: fisttpll (%esp)
+; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32_AVX1-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
+; X32_AVX1-NEXT: fildll {{[0-9]+}}(%esp)
+; X32_AVX1-NEXT: fstpl {{[0-9]+}}(%esp)
+; X32_AVX1-NEXT: fldl {{[0-9]+}}(%esp)
+; X32_AVX1-NEXT: movl %ebp, %esp
+; X32_AVX1-NEXT: popl %ebp
+; X32_AVX1-NEXT: .cfi_def_cfa %esp, 4
+; X32_AVX1-NEXT: retl
%i = fptosi double %x to i64
%r = sitofp i64 %i to double
ret double %r
@@ -392,10 +569,24 @@ define double @trunc_signed_f64_nsz(double %x) #0 {
; SSE41-NEXT: roundsd $11, %xmm0, %xmm0
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_signed_f64_nsz:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_signed_f64_nsz:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_signed_f64_nsz:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %ebp
+; X32_AVX1-NEXT: movl %esp, %ebp
+; X32_AVX1-NEXT: andl $-8, %esp
+; X32_AVX1-NEXT: subl $8, %esp
+; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32_AVX1-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovsd %xmm0, (%esp)
+; X32_AVX1-NEXT: fldl (%esp)
+; X32_AVX1-NEXT: movl %ebp, %esp
+; X32_AVX1-NEXT: popl %ebp
+; X32_AVX1-NEXT: retl
%i = fptosi double %x to i64
%r = sitofp i64 %i to double
ret double %r
@@ -413,10 +604,15 @@ define <4 x float> @trunc_signed_v4f32_nsz(<4 x float> %x) #0 {
; SSE41-NEXT: roundps $11, %xmm0, %xmm0
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_signed_v4f32_nsz:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundps $11, %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_signed_v4f32_nsz:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundps $11, %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_signed_v4f32_nsz:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: vroundps $11, %xmm0, %xmm0
+; X32_AVX1-NEXT: retl
%i = fptosi <4 x float> %x to <4 x i32>
%r = sitofp <4 x i32> %i to <4 x float>
ret <4 x float> %r
@@ -439,10 +635,15 @@ define <2 x double> @trunc_signed_v2f64_nsz(<2 x double> %x) #0 {
; SSE41-NEXT: roundpd $11, %xmm0, %xmm0
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_signed_v2f64_nsz:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundpd $11, %xmm0, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_signed_v2f64_nsz:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_signed_v2f64_nsz:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: vroundpd $11, %xmm0, %xmm0
+; X32_AVX1-NEXT: retl
%i = fptosi <2 x double> %x to <2 x i64>
%r = sitofp <2 x i64> %i to <2 x double>
ret <2 x double> %r
@@ -474,10 +675,15 @@ define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) #0 {
; SSE41-NEXT: roundpd $11, %xmm1, %xmm1
; SSE41-NEXT: retq
;
-; AVX1-LABEL: trunc_signed_v4f64_nsz:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vroundpd $11, %ymm0, %ymm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_signed_v4f64_nsz:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vroundpd $11, %ymm0, %ymm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_signed_v4f64_nsz:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: vroundpd $11, %ymm0, %ymm0
+; X32_AVX1-NEXT: retl
%i = fptosi <4 x double> %x to <4 x i64>
%r = sitofp <4 x i64> %i to <4 x double>
ret <4 x double> %r
@@ -495,12 +701,32 @@ define float @trunc_unsigned_f32_disable_via_attr(float %x) #1 {
; SSE-NEXT: cvtsi2ss %rax, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: trunc_unsigned_f32_disable_via_attr:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vcvttss2si %xmm0, %rax
-; AVX1-NEXT: movl %eax, %eax
-; AVX1-NEXT: vcvtsi2ss %rax, %xmm1, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_unsigned_f32_disable_via_attr:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vcvttss2si %xmm0, %rax
+; X64_AVX1-NEXT: movl %eax, %eax
+; X64_AVX1-NEXT: vcvtsi2ss %rax, %xmm1, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_unsigned_f32_disable_via_attr:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %eax
+; X32_AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32_AVX1-NEXT: vcvttss2si %xmm0, %eax
+; X32_AVX1-NEXT: movl %eax, %ecx
+; X32_AVX1-NEXT: sarl $31, %ecx
+; X32_AVX1-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32_AVX1-NEXT: vcvttss2si %xmm0, %edx
+; X32_AVX1-NEXT: andl %ecx, %edx
+; X32_AVX1-NEXT: orl %eax, %edx
+; X32_AVX1-NEXT: vmovd %edx, %xmm0
+; X32_AVX1-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32_AVX1-NEXT: vsubsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X32_AVX1-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0
+; X32_AVX1-NEXT: vmovss %xmm0, (%esp)
+; X32_AVX1-NEXT: flds (%esp)
+; X32_AVX1-NEXT: popl %eax
+; X32_AVX1-NEXT: retl
%i = fptoui float %x to i32
%r = uitofp i32 %i to float
ret float %r
@@ -514,11 +740,30 @@ define double @trunc_signed_f64_disable_via_attr(double %x) #1 {
; SSE-NEXT: cvtsi2sd %rax, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: trunc_signed_f64_disable_via_attr:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vcvttsd2si %xmm0, %rax
-; AVX1-NEXT: vcvtsi2sd %rax, %xmm1, %xmm0
-; AVX1-NEXT: retq
+; X64_AVX1-LABEL: trunc_signed_f64_disable_via_attr:
+; X64_AVX1: # %bb.0:
+; X64_AVX1-NEXT: vcvttsd2si %xmm0, %rax
+; X64_AVX1-NEXT: vcvtsi2sd %rax, %xmm1, %xmm0
+; X64_AVX1-NEXT: retq
+;
+; X32_AVX1-LABEL: trunc_signed_f64_disable_via_attr:
+; X32_AVX1: # %bb.0:
+; X32_AVX1-NEXT: pushl %ebp
+; X32_AVX1-NEXT: movl %esp, %ebp
+; X32_AVX1-NEXT: andl $-8, %esp
+; X32_AVX1-NEXT: subl $24, %esp
+; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32_AVX1-NEXT: vmovsd %xmm0, (%esp)
+; X32_AVX1-NEXT: fldl (%esp)
+; X32_AVX1-NEXT: fisttpll (%esp)
+; X32_AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32_AVX1-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
+; X32_AVX1-NEXT: fildll {{[0-9]+}}(%esp)
+; X32_AVX1-NEXT: fstpl {{[0-9]+}}(%esp)
+; X32_AVX1-NEXT: fldl {{[0-9]+}}(%esp)
+; X32_AVX1-NEXT: movl %ebp, %esp
+; X32_AVX1-NEXT: popl %ebp
+; X32_AVX1-NEXT: retl
%i = fptosi double %x to i64
%r = sitofp i64 %i to double
ret double %r
More information about the llvm-commits
mailing list