[PATCH] D115881: [WIP][AMDGPU][GlobalISel] Add patterns for no-return atomic ops with single address and data in tblgen.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/DSInstructions.td:138
+}
+
 multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
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You shouldn't need to change or introduce new opcodes, we have them already


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115881/new/

https://reviews.llvm.org/D115881