[llvm] b8c9ebf - [AArch64] Regenerate concat_vector-truncate-combine.ll tests

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 17 05:59:39 PST 2021


Author: Simon Pilgrim
Date: 2021-12-17T13:59:19Z
New Revision: b8c9ebfac89857e4a3bb6602d6567b0954b31011

URL: https://github.com/llvm/llvm-project/commit/b8c9ebfac89857e4a3bb6602d6567b0954b31011
DIFF: https://github.com/llvm/llvm-project/commit/b8c9ebfac89857e4a3bb6602d6567b0954b31011.diff

LOG: [AArch64] Regenerate concat_vector-truncate-combine.ll tests

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll b/llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
index 6b788b4e1d9a..b582d42c4131 100644
--- a/llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
+++ b/llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
@@ -1,15 +1,17 @@
-; RUN: llc < %s -mtriple arm64-apple-darwin -asm-verbose=false | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple arm64-- | FileCheck %s
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
 ; Test the (concat_vectors (trunc), (trunc)) pattern.
 
 define <4 x i16> @test_concat_truncate_v2i64_to_v4i16(<2 x i64> %a, <2 x i64> %b) #0 {
-entry:
 ; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i16:
-; CHECK-NEXT: uzp1.4s v0, v0, v1
-; CHECK-NEXT: xtn.4h v0, v0
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
+; CHECK-NEXT:    ret
+entry:
   %at = trunc <2 x i64> %a to <2 x i16>
   %bt = trunc <2 x i64> %b to <2 x i16>
   %shuffle = shufflevector <2 x i16> %at, <2 x i16> %bt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -17,10 +19,11 @@ entry:
 }
 
 define <4 x i32> @test_concat_truncate_v2i64_to_v4i32(<2 x i64> %a, <2 x i64> %b) #0 {
-entry:
 ; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i32:
-; CHECK-NEXT: uzp1.4s v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    ret
+entry:
   %at = trunc <2 x i64> %a to <2 x i32>
   %bt = trunc <2 x i64> %b to <2 x i32>
   %shuffle = shufflevector <2 x i32> %at, <2 x i32> %bt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -28,10 +31,11 @@ entry:
 }
 
 define <4 x i16> @test_concat_truncate_v2i32_to_v4i16(<2 x i32> %a, <2 x i32> %b) #0 {
-entry:
 ; CHECK-LABEL: test_concat_truncate_v2i32_to_v4i16:
-; CHECK-NEXT: uzp1.4h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-NEXT:    ret
+entry:
   %at = trunc <2 x i32> %a to <2 x i16>
   %bt = trunc <2 x i32> %b to <2 x i16>
   %shuffle = shufflevector <2 x i16> %at, <2 x i16> %bt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -39,11 +43,12 @@ entry:
 }
 
 define <8 x i8> @test_concat_truncate_v4i32_to_v8i8(<4 x i32> %a, <4 x i32> %b) #0 {
-entry:
 ; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i8:
-; CHECK-NEXT: uzp1.8h v0, v0, v1
-; CHECK-NEXT: xtn.8b v0, v0
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    xtn v0.8b, v0.8h
+; CHECK-NEXT:    ret
+entry:
   %at = trunc <4 x i32> %a to <4 x i8>
   %bt = trunc <4 x i32> %b to <4 x i8>
   %shuffle = shufflevector <4 x i8> %at, <4 x i8> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -51,10 +56,11 @@ entry:
 }
 
 define <8 x i16> @test_concat_truncate_v4i32_to_v8i16(<4 x i32> %a, <4 x i32> %b) #0 {
-entry:
 ; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i16:
-; CHECK-NEXT: uzp1.8h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    ret
+entry:
   %at = trunc <4 x i32> %a to <4 x i16>
   %bt = trunc <4 x i32> %b to <4 x i16>
   %shuffle = shufflevector <4 x i16> %at, <4 x i16> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -62,10 +68,11 @@ entry:
 }
 
 define <8 x i8> @test_concat_truncate_v4i16_to_v8i8(<4 x i16> %a, <4 x i16> %b) #0 {
-entry:
 ; CHECK-LABEL: test_concat_truncate_v4i16_to_v8i8:
-; CHECK-NEXT: uzp1.8b v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uzp1 v0.8b, v0.8b, v1.8b
+; CHECK-NEXT:    ret
+entry:
   %at = trunc <4 x i16> %a to <4 x i8>
   %bt = trunc <4 x i16> %b to <4 x i8>
   %shuffle = shufflevector <4 x i8> %at, <4 x i8> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -73,10 +80,11 @@ entry:
 }
 
 define <16 x i8> @test_concat_truncate_v8i16_to_v16i8(<8 x i16> %a, <8 x i16> %b) #0 {
-entry:
 ; CHECK-LABEL: test_concat_truncate_v8i16_to_v16i8:
-; CHECK-NEXT: uzp1.16b v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uzp1 v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
   %at = trunc <8 x i16> %a to <8 x i8>
   %bt = trunc <8 x i16> %b to <8 x i8>
   %shuffle = shufflevector <8 x i8> %at, <8 x i8> %bt, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32  9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -86,15 +94,16 @@ entry:
 ; The concat_vectors operation in this test is introduced when splitting
 ; the fptrunc operation due to the split <vscale x 4 x double> input operand.
 define void @test_concat_fptrunc_v4f64_to_v4f32(<vscale x 4 x float>* %ptr) #1 {
-entry:
 ; CHECK-LABEL: test_concat_fptrunc_v4f64_to_v4f32:
-; CHECK:       fmov    z0.d, #1.00000000
-; CHECK-NEXT:  ptrue   p0.d
-; CHECK-NEXT:  fcvt    z0.s, p0/m, z0.d
-; CHECK-NEXT:  ptrue   p0.s
-; CHECK-NEXT:  uzp1    z0.s, z0.s, z0.s
-; CHECK-NEXT:  st1w    { z0.s }, p0, [x0]
-; CHECK-NEXT:  ret
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fmov z0.d, #1.00000000
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fcvt z0.s, p0/m, z0.d
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
+; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
+; CHECK-NEXT:    ret
+entry:
   %0 = shufflevector <vscale x 4 x double> insertelement (<vscale x 4 x double> poison, double 1.000000e+00, i32 0), <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
   %1 = fptrunc <vscale x 4 x double> %0 to <vscale x 4 x float>
   store <vscale x 4 x float> %1, <vscale x 4 x float>* %ptr, align 4


        


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