[PATCH] D113183: [LV] Patch up induction phis after VPlan execution.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


================
Comment at: llvm/lib/Transforms/Vectorize/VPlan.h:1015
+  /// modeling the increment  explicitly in VPlan.
+  Instruction *LastInduction = nullptr;
+
----------------
Ayal wrote:
> fhahn wrote:
> > Ayal wrote:
> > > Better rename `LastInduction` to "LastIncrementOfVectorIV", throughout?
> > > 
> > > Scalar IV's are generated w/o a cross-iteration increment, based off of `Induction`, which is pre-generated as part of the skeleton, along with its last increment in the latch.
> > > 
> > > An alternative of forming a Region with an Exit to represent the latch, is mentioned in D114586.
> > > Better rename LastInduction to "LastIncrementOfVectorIV", throughout?
> > 
> > Done, thanks!
> > 
> > > An alternative of forming a Region with an Exit to represent the latch, is mentioned in D114586.
> > 
> > I'll follow up on the suggestion, but I don't see how this is related directly to this patch. Future patches will remove the need to keeping the last induction increment here by modeling the increment explicitly in VPlan. But to support the general induction case, we need to support expand the step for the induction from a SCEV expression in the pre-header. I'll put patches up to do this once we can model the pre-header.
> >> An alternative of forming a Region with an Exit to represent the latch, is mentioned in D114586.
> > ... how this is related directly to this patch
> This alternative may have two (alternative?) parts:
> Having the Exit VPBasicBlock available when creating header phi recipes will enable placing last increments there to begin with, instead of moving them (or their generated IR Instruction). This requires introducing recipes/VPInstructions to model these increments, as proposed in follow-up D113223, so indeed more directly related to that patch.
> Having the IR Latch BasicBlock available when header phi recipes execute will enable them to generate their last increments and rewire them there and then, w/o needing to record and rewire later. This requires generating the IR basic block of the latch along with that of the header, presumably by VPRegionBase::execute(). But instead of having induction header-phi  recipes be responsible for generating their entire chain of increments, it may be better if they behave like reduction and FOR header-phi recipes, whose 'previous' or last reduction operations have independent recipes; this supports a simple linear code-generation of VPlan, instead of moving a builder's insert position around.
Patch to introduce header & latch up front is available now: D115793

I'll see how this may shake out in terms of simplifications here.


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  https://reviews.llvm.org/D113183/new/

https://reviews.llvm.org/D113183