[llvm] 0019149 - [RISCV] Rename Zbs test cases to match instruction names. NFC

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 15 11:08:26 PST 2021


Author: Craig Topper
Date: 2021-12-15T11:08:05-08:00
New Revision: 001914975db18c75cb05edc6b7f5b2f3eaf4b871

URL: https://github.com/llvm/llvm-project/commit/001914975db18c75cb05edc6b7f5b2f3eaf4b871
DIFF: https://github.com/llvm/llvm-project/commit/001914975db18c75cb05edc6b7f5b2f3eaf4b871.diff

LOG: [RISCV] Rename Zbs test cases to match instruction names. NFC

The Zbs instructions uses to start with 'sb' but now start with 'b'.
Update test names accordingly.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv32zbs.ll
    llvm/test/CodeGen/RISCV/rv64zbs.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll
index 9730a160f7cf..08076b06f117 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll
@@ -4,8 +4,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32ZBS
 
-define i32 @sbclr_i32(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sbclr_i32:
+define i32 @bclr_i32(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: bclr_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a2, 1
 ; RV32I-NEXT:    sll a1, a2, a1
@@ -13,7 +13,7 @@ define i32 @sbclr_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclr_i32:
+; RV32ZBS-LABEL: bclr_i32:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bclr a0, a0, a1
 ; RV32ZBS-NEXT:    ret
@@ -24,8 +24,8 @@ define i32 @sbclr_i32(i32 %a, i32 %b) nounwind {
   ret i32 %and1
 }
 
-define i32 @sbclr_i32_no_mask(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sbclr_i32_no_mask:
+define i32 @bclr_i32_no_mask(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: bclr_i32_no_mask:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a2, 1
 ; RV32I-NEXT:    sll a1, a2, a1
@@ -33,7 +33,7 @@ define i32 @sbclr_i32_no_mask(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclr_i32_no_mask:
+; RV32ZBS-LABEL: bclr_i32_no_mask:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bclr a0, a0, a1
 ; RV32ZBS-NEXT:    ret
@@ -43,8 +43,8 @@ define i32 @sbclr_i32_no_mask(i32 %a, i32 %b) nounwind {
   ret i32 %and1
 }
 
-define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
-; RV32I-LABEL: sbclr_i64:
+define i64 @bclr_i64(i64 %a, i64 %b) nounwind {
+; RV32I-LABEL: bclr_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a3, a2, 63
 ; RV32I-NEXT:    addi a4, a3, -32
@@ -61,7 +61,7 @@ define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-NEXT:    and a0, a0, a2
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclr_i64:
+; RV32ZBS-LABEL: bclr_i64:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    andi a3, a2, 63
 ; RV32ZBS-NEXT:    addi a3, a3, -32
@@ -79,15 +79,15 @@ define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
   ret i64 %and1
 }
 
-define i32 @sbset_i32(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sbset_i32:
+define i32 @bset_i32(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: bset_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a2, 1
 ; RV32I-NEXT:    sll a1, a2, a1
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbset_i32:
+; RV32ZBS-LABEL: bset_i32:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bset a0, a0, a1
 ; RV32ZBS-NEXT:    ret
@@ -97,15 +97,15 @@ define i32 @sbset_i32(i32 %a, i32 %b) nounwind {
   ret i32 %or
 }
 
-define i32 @sbset_i32_no_mask(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sbset_i32_no_mask:
+define i32 @bset_i32_no_mask(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: bset_i32_no_mask:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a2, 1
 ; RV32I-NEXT:    sll a1, a2, a1
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbset_i32_no_mask:
+; RV32ZBS-LABEL: bset_i32_no_mask:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bset a0, a0, a1
 ; RV32ZBS-NEXT:    ret
@@ -114,15 +114,15 @@ define i32 @sbset_i32_no_mask(i32 %a, i32 %b) nounwind {
   ret i32 %or
 }
 
-; We can use sbsetw for 1 << x by setting the first source to zero.
-define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
-; RV32I-LABEL: sbset_i32_zero:
+; We can use bsetw for 1 << x by setting the first source to zero.
+define signext i32 @bset_i32_zero(i32 signext %a) nounwind {
+; RV32I-LABEL: bset_i32_zero:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a1, 1
 ; RV32I-NEXT:    sll a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbset_i32_zero:
+; RV32ZBS-LABEL: bset_i32_zero:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bset a0, zero, a0
 ; RV32ZBS-NEXT:    ret
@@ -135,8 +135,8 @@ define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
 ; This test is presented here in case future expansions of the experimental-b
 ; extension introduce instructions suitable for this pattern.
 
-define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
-; RV32I-LABEL: sbset_i64:
+define i64 @bset_i64(i64 %a, i64 %b) nounwind {
+; RV32I-LABEL: bset_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a3, 1
 ; RV32I-NEXT:    sll a2, a3, a2
@@ -145,7 +145,7 @@ define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-NEXT:    or a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbset_i64:
+; RV32ZBS-LABEL: bset_i64:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bset a3, zero, a2
 ; RV32ZBS-NEXT:    srai a3, a3, 31
@@ -160,8 +160,8 @@ define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
   ret i64 %or
 }
 
-define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
-; RV32I-LABEL: sbset_i64_zero:
+define signext i64 @bset_i64_zero(i64 signext %a) nounwind {
+; RV32I-LABEL: bset_i64_zero:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, a0, -32
 ; RV32I-NEXT:    li a2, 1
@@ -175,7 +175,7 @@ define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
 ; RV32I-NEXT:    sll a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbset_i64_zero:
+; RV32ZBS-LABEL: bset_i64_zero:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    addi a1, a0, -32
 ; RV32ZBS-NEXT:    bltz a1, .LBB7_2
@@ -191,15 +191,15 @@ define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
   ret i64 %shl
 }
 
-define i32 @sbinv_i32(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sbinv_i32:
+define i32 @binv_i32(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: binv_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a2, 1
 ; RV32I-NEXT:    sll a1, a2, a1
 ; RV32I-NEXT:    xor a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbinv_i32:
+; RV32ZBS-LABEL: binv_i32:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    binv a0, a0, a1
 ; RV32ZBS-NEXT:    ret
@@ -214,8 +214,8 @@ define i32 @sbinv_i32(i32 %a, i32 %b) nounwind {
 ; This test is presented here in case future expansions of the experimental-b
 ; extension introduce instructions suitable for this pattern.
 
-define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
-; RV32I-LABEL: sbinv_i64:
+define i64 @binv_i64(i64 %a, i64 %b) nounwind {
+; RV32I-LABEL: binv_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a3, 1
 ; RV32I-NEXT:    sll a2, a3, a2
@@ -224,7 +224,7 @@ define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-NEXT:    xor a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbinv_i64:
+; RV32ZBS-LABEL: binv_i64:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bset a3, zero, a2
 ; RV32ZBS-NEXT:    srai a3, a3, 31
@@ -239,14 +239,14 @@ define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
   ret i64 %xor
 }
 
-define i32 @sbext_i32(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sbext_i32:
+define i32 @bext_i32(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: bext_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srl a0, a0, a1
 ; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbext_i32:
+; RV32ZBS-LABEL: bext_i32:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bext a0, a0, a1
 ; RV32ZBS-NEXT:    ret
@@ -256,14 +256,14 @@ define i32 @sbext_i32(i32 %a, i32 %b) nounwind {
   ret i32 %and1
 }
 
-define i32 @sbext_i32_no_mask(i32 %a, i32 %b) nounwind {
-; RV32I-LABEL: sbext_i32_no_mask:
+define i32 @bext_i32_no_mask(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: bext_i32_no_mask:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srl a0, a0, a1
 ; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbext_i32_no_mask:
+; RV32ZBS-LABEL: bext_i32_no_mask:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bext a0, a0, a1
 ; RV32ZBS-NEXT:    ret
@@ -277,8 +277,8 @@ define i32 @sbext_i32_no_mask(i32 %a, i32 %b) nounwind {
 ; This test is presented here in case future expansions of the experimental-b
 ; extension introduce instructions suitable for this pattern.
 
-define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
-; RV32I-LABEL: sbext_i64:
+define i64 @bext_i64(i64 %a, i64 %b) nounwind {
+; RV32I-LABEL: bext_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a3, a2, 63
 ; RV32I-NEXT:    addi a4, a3, -32
@@ -298,7 +298,7 @@ define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbext_i64:
+; RV32ZBS-LABEL: bext_i64:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    andi a3, a2, 63
 ; RV32ZBS-NEXT:    addi a4, a3, -32
@@ -323,14 +323,14 @@ define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
   ret i64 %and1
 }
 
-define i32 @sbexti_i32(i32 %a) nounwind {
-; RV32I-LABEL: sbexti_i32:
+define i32 @bexti_i32(i32 %a) nounwind {
+; RV32I-LABEL: bexti_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a0, a0, 5
 ; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbexti_i32:
+; RV32ZBS-LABEL: bexti_i32:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bexti a0, a0, 5
 ; RV32ZBS-NEXT:    ret
@@ -339,15 +339,15 @@ define i32 @sbexti_i32(i32 %a) nounwind {
   ret i32 %and
 }
 
-define i64 @sbexti_i64(i64 %a) nounwind {
-; RV32I-LABEL: sbexti_i64:
+define i64 @bexti_i64(i64 %a) nounwind {
+; RV32I-LABEL: bexti_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a0, a0, 5
 ; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbexti_i64:
+; RV32ZBS-LABEL: bexti_i64:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bexti a0, a0, 5
 ; RV32ZBS-NEXT:    li a1, 0
@@ -357,13 +357,13 @@ define i64 @sbexti_i64(i64 %a) nounwind {
   ret i64 %and
 }
 
-define i32 @sbclri_i32_10(i32 %a) nounwind {
-; RV32I-LABEL: sbclri_i32_10:
+define i32 @bclri_i32_10(i32 %a) nounwind {
+; RV32I-LABEL: bclri_i32_10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a0, a0, -1025
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclri_i32_10:
+; RV32ZBS-LABEL: bclri_i32_10:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    andi a0, a0, -1025
 ; RV32ZBS-NEXT:    ret
@@ -371,15 +371,15 @@ define i32 @sbclri_i32_10(i32 %a) nounwind {
   ret i32 %and
 }
 
-define i32 @sbclri_i32_11(i32 %a) nounwind {
-; RV32I-LABEL: sbclri_i32_11:
+define i32 @bclri_i32_11(i32 %a) nounwind {
+; RV32I-LABEL: bclri_i32_11:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1048575
 ; RV32I-NEXT:    addi a1, a1, 2047
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclri_i32_11:
+; RV32ZBS-LABEL: bclri_i32_11:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bclri a0, a0, 11
 ; RV32ZBS-NEXT:    ret
@@ -387,15 +387,15 @@ define i32 @sbclri_i32_11(i32 %a) nounwind {
   ret i32 %and
 }
 
-define i32 @sbclri_i32_30(i32 %a) nounwind {
-; RV32I-LABEL: sbclri_i32_30:
+define i32 @bclri_i32_30(i32 %a) nounwind {
+; RV32I-LABEL: bclri_i32_30:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 786432
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclri_i32_30:
+; RV32ZBS-LABEL: bclri_i32_30:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bclri a0, a0, 30
 ; RV32ZBS-NEXT:    ret
@@ -403,15 +403,15 @@ define i32 @sbclri_i32_30(i32 %a) nounwind {
   ret i32 %and
 }
 
-define i32 @sbclri_i32_31(i32 %a) nounwind {
-; RV32I-LABEL: sbclri_i32_31:
+define i32 @bclri_i32_31(i32 %a) nounwind {
+; RV32I-LABEL: bclri_i32_31:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclri_i32_31:
+; RV32ZBS-LABEL: bclri_i32_31:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bclri a0, a0, 31
 ; RV32ZBS-NEXT:    ret
@@ -419,15 +419,15 @@ define i32 @sbclri_i32_31(i32 %a) nounwind {
   ret i32 %and
 }
 
-define i32 @sbclri_i32_large0(i32 %a) nounwind {
-; RV32I-LABEL: sbclri_i32_large0:
+define i32 @bclri_i32_large0(i32 %a) nounwind {
+; RV32I-LABEL: bclri_i32_large0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1044480
 ; RV32I-NEXT:    addi a1, a1, -256
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclri_i32_large0:
+; RV32ZBS-LABEL: bclri_i32_large0:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    andi a0, a0, -256
 ; RV32ZBS-NEXT:    bclri a0, a0, 24
@@ -436,15 +436,15 @@ define i32 @sbclri_i32_large0(i32 %a) nounwind {
   ret i32 %and
 }
 
-define i32 @sbclri_i32_large1(i32 %a) nounwind {
-; RV32I-LABEL: sbclri_i32_large1:
+define i32 @bclri_i32_large1(i32 %a) nounwind {
+; RV32I-LABEL: bclri_i32_large1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1044464
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclri_i32_large1:
+; RV32ZBS-LABEL: bclri_i32_large1:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bclri a0, a0, 16
 ; RV32ZBS-NEXT:    bclri a0, a0, 24
@@ -453,15 +453,15 @@ define i32 @sbclri_i32_large1(i32 %a) nounwind {
   ret i32 %and
 }
 
-define i32 @sbclri_i32_large2(i32 %0) {
-; RV32I-LABEL: sbclri_i32_large2:
+define i32 @bclri_i32_large2(i32 %0) {
+; RV32I-LABEL: bclri_i32_large2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    addi a1, a1, -5
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclri_i32_large2:
+; RV32ZBS-LABEL: bclri_i32_large2:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bclri a0, a0, 2
 ; RV32ZBS-NEXT:    bclri a0, a0, 31
@@ -470,15 +470,15 @@ define i32 @sbclri_i32_large2(i32 %0) {
   ret i32 %2
 }
 
-define i32 @sbclri_i32_large3(i32 %0) {
-; RV32I-LABEL: sbclri_i32_large3:
+define i32 @bclri_i32_large3(i32 %0) {
+; RV32I-LABEL: bclri_i32_large3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    addi a1, a1, -6
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbclri_i32_large3:
+; RV32ZBS-LABEL: bclri_i32_large3:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    andi a0, a0, -6
 ; RV32ZBS-NEXT:    bclri a0, a0, 31
@@ -487,13 +487,13 @@ define i32 @sbclri_i32_large3(i32 %0) {
   ret i32 %2
 }
 
-define i32 @sbseti_i32_10(i32 %a) nounwind {
-; RV32I-LABEL: sbseti_i32_10:
+define i32 @bseti_i32_10(i32 %a) nounwind {
+; RV32I-LABEL: bseti_i32_10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ori a0, a0, 1024
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbseti_i32_10:
+; RV32ZBS-LABEL: bseti_i32_10:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    ori a0, a0, 1024
 ; RV32ZBS-NEXT:    ret
@@ -501,15 +501,15 @@ define i32 @sbseti_i32_10(i32 %a) nounwind {
   ret i32 %or
 }
 
-define i32 @sbseti_i32_11(i32 %a) nounwind {
-; RV32I-LABEL: sbseti_i32_11:
+define i32 @bseti_i32_11(i32 %a) nounwind {
+; RV32I-LABEL: bseti_i32_11:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, -2048
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbseti_i32_11:
+; RV32ZBS-LABEL: bseti_i32_11:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bseti a0, a0, 11
 ; RV32ZBS-NEXT:    ret
@@ -517,14 +517,14 @@ define i32 @sbseti_i32_11(i32 %a) nounwind {
   ret i32 %or
 }
 
-define i32 @sbseti_i32_30(i32 %a) nounwind {
-; RV32I-LABEL: sbseti_i32_30:
+define i32 @bseti_i32_30(i32 %a) nounwind {
+; RV32I-LABEL: bseti_i32_30:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 262144
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbseti_i32_30:
+; RV32ZBS-LABEL: bseti_i32_30:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bseti a0, a0, 30
 ; RV32ZBS-NEXT:    ret
@@ -532,14 +532,14 @@ define i32 @sbseti_i32_30(i32 %a) nounwind {
   ret i32 %or
 }
 
-define i32 @sbseti_i32_31(i32 %a) nounwind {
-; RV32I-LABEL: sbseti_i32_31:
+define i32 @bseti_i32_31(i32 %a) nounwind {
+; RV32I-LABEL: bseti_i32_31:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbseti_i32_31:
+; RV32ZBS-LABEL: bseti_i32_31:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bseti a0, a0, 31
 ; RV32ZBS-NEXT:    ret
@@ -547,13 +547,13 @@ define i32 @sbseti_i32_31(i32 %a) nounwind {
   ret i32 %or
 }
 
-define i32 @sbinvi_i32_10(i32 %a) nounwind {
-; RV32I-LABEL: sbinvi_i32_10:
+define i32 @binvi_i32_10(i32 %a) nounwind {
+; RV32I-LABEL: binvi_i32_10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xori a0, a0, 1024
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbinvi_i32_10:
+; RV32ZBS-LABEL: binvi_i32_10:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    xori a0, a0, 1024
 ; RV32ZBS-NEXT:    ret
@@ -561,15 +561,15 @@ define i32 @sbinvi_i32_10(i32 %a) nounwind {
   ret i32 %xor
 }
 
-define i32 @sbinvi_i32_11(i32 %a) nounwind {
-; RV32I-LABEL: sbinvi_i32_11:
+define i32 @binvi_i32_11(i32 %a) nounwind {
+; RV32I-LABEL: binvi_i32_11:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, -2048
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbinvi_i32_11:
+; RV32ZBS-LABEL: binvi_i32_11:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    binvi a0, a0, 11
 ; RV32ZBS-NEXT:    ret
@@ -577,14 +577,14 @@ define i32 @sbinvi_i32_11(i32 %a) nounwind {
   ret i32 %xor
 }
 
-define i32 @sbinvi_i32_30(i32 %a) nounwind {
-; RV32I-LABEL: sbinvi_i32_30:
+define i32 @binvi_i32_30(i32 %a) nounwind {
+; RV32I-LABEL: binvi_i32_30:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 262144
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbinvi_i32_30:
+; RV32ZBS-LABEL: binvi_i32_30:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    binvi a0, a0, 30
 ; RV32ZBS-NEXT:    ret
@@ -592,14 +592,14 @@ define i32 @sbinvi_i32_30(i32 %a) nounwind {
   ret i32 %xor
 }
 
-define i32 @sbinvi_i32_31(i32 %a) nounwind {
-; RV32I-LABEL: sbinvi_i32_31:
+define i32 @binvi_i32_31(i32 %a) nounwind {
+; RV32I-LABEL: binvi_i32_31:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBS-LABEL: sbinvi_i32_31:
+; RV32ZBS-LABEL: binvi_i32_31:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    binvi a0, a0, 31
 ; RV32ZBS-NEXT:    ret

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64zbs.ll
index 251f3cf0bf0a..1f3efb5b9d19 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbs.ll
@@ -4,8 +4,8 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZBS
 
-define signext i32 @sbclr_i32(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sbclr_i32:
+define signext i32 @bclr_i32(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: bclr_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
@@ -13,7 +13,7 @@ define signext i32 @sbclr_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclr_i32:
+; RV64ZBS-LABEL: bclr_i32:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    li a2, 1
 ; RV64ZBS-NEXT:    sllw a1, a2, a1
@@ -27,8 +27,8 @@ define signext i32 @sbclr_i32(i32 signext %a, i32 signext %b) nounwind {
   ret i32 %and1
 }
 
-define signext i32 @sbclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sbclr_i32_no_mask:
+define signext i32 @bclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: bclr_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
@@ -36,7 +36,7 @@ define signext i32 @sbclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclr_i32_no_mask:
+; RV64ZBS-LABEL: bclr_i32_no_mask:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    li a2, 1
 ; RV64ZBS-NEXT:    sllw a1, a2, a1
@@ -49,8 +49,8 @@ define signext i32 @sbclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
   ret i32 %and1
 }
 
-define signext i32 @sbclr_i32_load(i32* %p, i32 signext %b) nounwind {
-; RV64I-LABEL: sbclr_i32_load:
+define signext i32 @bclr_i32_load(i32* %p, i32 signext %b) nounwind {
+; RV64I-LABEL: bclr_i32_load:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    li a2, 1
@@ -60,7 +60,7 @@ define signext i32 @sbclr_i32_load(i32* %p, i32 signext %b) nounwind {
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclr_i32_load:
+; RV64ZBS-LABEL: bclr_i32_load:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lw a0, 0(a0)
 ; RV64ZBS-NEXT:    li a2, 1
@@ -76,8 +76,8 @@ define signext i32 @sbclr_i32_load(i32* %p, i32 signext %b) nounwind {
   ret i32 %and1
 }
 
-define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: sbclr_i64:
+define i64 @bclr_i64(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: bclr_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sll a1, a2, a1
@@ -85,7 +85,7 @@ define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclr_i64:
+; RV64ZBS-LABEL: bclr_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclr a0, a0, a1
 ; RV64ZBS-NEXT:    ret
@@ -96,8 +96,8 @@ define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
   ret i64 %and1
 }
 
-define i64 @sbclr_i64_no_mask(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: sbclr_i64_no_mask:
+define i64 @bclr_i64_no_mask(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: bclr_i64_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sll a1, a2, a1
@@ -105,7 +105,7 @@ define i64 @sbclr_i64_no_mask(i64 %a, i64 %b) nounwind {
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclr_i64_no_mask:
+; RV64ZBS-LABEL: bclr_i64_no_mask:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclr a0, a0, a1
 ; RV64ZBS-NEXT:    ret
@@ -115,15 +115,15 @@ define i64 @sbclr_i64_no_mask(i64 %a, i64 %b) nounwind {
   ret i64 %and1
 }
 
-define signext i32 @sbset_i32(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sbset_i32:
+define signext i32 @bset_i32(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: bset_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbset_i32:
+; RV64ZBS-LABEL: bset_i32:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    li a2, 1
 ; RV64ZBS-NEXT:    sllw a1, a2, a1
@@ -135,15 +135,15 @@ define signext i32 @sbset_i32(i32 signext %a, i32 signext %b) nounwind {
   ret i32 %or
 }
 
-define signext i32 @sbset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sbset_i32_no_mask:
+define signext i32 @bset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: bset_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbset_i32_no_mask:
+; RV64ZBS-LABEL: bset_i32_no_mask:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    li a2, 1
 ; RV64ZBS-NEXT:    sllw a1, a2, a1
@@ -154,8 +154,8 @@ define signext i32 @sbset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
   ret i32 %or
 }
 
-define signext i32 @sbset_i32_load(i32* %p, i32 signext %b) nounwind {
-; RV64I-LABEL: sbset_i32_load:
+define signext i32 @bset_i32_load(i32* %p, i32 signext %b) nounwind {
+; RV64I-LABEL: bset_i32_load:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    li a2, 1
@@ -164,7 +164,7 @@ define signext i32 @sbset_i32_load(i32* %p, i32 signext %b) nounwind {
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbset_i32_load:
+; RV64ZBS-LABEL: bset_i32_load:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lw a0, 0(a0)
 ; RV64ZBS-NEXT:    li a2, 1
@@ -178,15 +178,15 @@ define signext i32 @sbset_i32_load(i32* %p, i32 signext %b) nounwind {
   ret i32 %or
 }
 
-; We can use sbsetw for 1 << x by setting the first source to zero.
-define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
-; RV64I-LABEL: sbset_i32_zero:
+; We can use bsetw for 1 << x by setting the first source to zero.
+define signext i32 @bset_i32_zero(i32 signext %a) nounwind {
+; RV64I-LABEL: bset_i32_zero:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, 1
 ; RV64I-NEXT:    sllw a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbset_i32_zero:
+; RV64ZBS-LABEL: bset_i32_zero:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    li a1, 1
 ; RV64ZBS-NEXT:    sllw a0, a1, a0
@@ -195,15 +195,15 @@ define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
   ret i32 %shl
 }
 
-define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: sbset_i64:
+define i64 @bset_i64(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: bset_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sll a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbset_i64:
+; RV64ZBS-LABEL: bset_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bset a0, a0, a1
 ; RV64ZBS-NEXT:    ret
@@ -213,15 +213,15 @@ define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
   ret i64 %or
 }
 
-define i64 @sbset_i64_no_mask(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: sbset_i64_no_mask:
+define i64 @bset_i64_no_mask(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: bset_i64_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sll a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbset_i64_no_mask:
+; RV64ZBS-LABEL: bset_i64_no_mask:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bset a0, a0, a1
 ; RV64ZBS-NEXT:    ret
@@ -230,15 +230,15 @@ define i64 @sbset_i64_no_mask(i64 %a, i64 %b) nounwind {
   ret i64 %or
 }
 
-; We can use sbsetw for 1 << x by setting the first source to zero.
-define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
-; RV64I-LABEL: sbset_i64_zero:
+; We can use bsetw for 1 << x by setting the first source to zero.
+define signext i64 @bset_i64_zero(i64 signext %a) nounwind {
+; RV64I-LABEL: bset_i64_zero:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, 1
 ; RV64I-NEXT:    sll a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbset_i64_zero:
+; RV64ZBS-LABEL: bset_i64_zero:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bset a0, zero, a0
 ; RV64ZBS-NEXT:    ret
@@ -246,15 +246,15 @@ define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
   ret i64 %shl
 }
 
-define signext i32 @sbinv_i32(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sbinv_i32:
+define signext i32 @binv_i32(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: binv_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinv_i32:
+; RV64ZBS-LABEL: binv_i32:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    li a2, 1
 ; RV64ZBS-NEXT:    sllw a1, a2, a1
@@ -266,15 +266,15 @@ define signext i32 @sbinv_i32(i32 signext %a, i32 signext %b) nounwind {
   ret i32 %xor
 }
 
-define signext i32 @sbinv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sbinv_i32_no_mask:
+define signext i32 @binv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: binv_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinv_i32_no_mask:
+; RV64ZBS-LABEL: binv_i32_no_mask:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    li a2, 1
 ; RV64ZBS-NEXT:    sllw a1, a2, a1
@@ -285,8 +285,8 @@ define signext i32 @sbinv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
   ret i32 %xor
 }
 
-define signext i32 @sbinv_i32_load(i32* %p, i32 signext %b) nounwind {
-; RV64I-LABEL: sbinv_i32_load:
+define signext i32 @binv_i32_load(i32* %p, i32 signext %b) nounwind {
+; RV64I-LABEL: binv_i32_load:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    li a2, 1
@@ -295,7 +295,7 @@ define signext i32 @sbinv_i32_load(i32* %p, i32 signext %b) nounwind {
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinv_i32_load:
+; RV64ZBS-LABEL: binv_i32_load:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lw a0, 0(a0)
 ; RV64ZBS-NEXT:    li a2, 1
@@ -309,15 +309,15 @@ define signext i32 @sbinv_i32_load(i32* %p, i32 signext %b) nounwind {
   ret i32 %xor
 }
 
-define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: sbinv_i64:
+define i64 @binv_i64(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: binv_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sll a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinv_i64:
+; RV64ZBS-LABEL: binv_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binv a0, a0, a1
 ; RV64ZBS-NEXT:    ret
@@ -327,15 +327,15 @@ define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
   ret i64 %xor
 }
 
-define i64 @sbinv_i64_no_mask(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: sbinv_i64_no_mask:
+define i64 @binv_i64_no_mask(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: binv_i64_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sll a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinv_i64_no_mask:
+; RV64ZBS-LABEL: binv_i64_no_mask:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binv a0, a0, a1
 ; RV64ZBS-NEXT:    ret
@@ -344,14 +344,14 @@ define i64 @sbinv_i64_no_mask(i64 %a, i64 %b) nounwind {
   ret i64 %xor
 }
 
-define signext i32 @sbext_i32(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sbext_i32:
+define signext i32 @bext_i32(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: bext_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbext_i32:
+; RV64ZBS-LABEL: bext_i32:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    srlw a0, a0, a1
 ; RV64ZBS-NEXT:    andi a0, a0, 1
@@ -362,14 +362,14 @@ define signext i32 @sbext_i32(i32 signext %a, i32 signext %b) nounwind {
   ret i32 %and1
 }
 
-define signext i32 @sbext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: sbext_i32_no_mask:
+define signext i32 @bext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: bext_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbext_i32_no_mask:
+; RV64ZBS-LABEL: bext_i32_no_mask:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    srlw a0, a0, a1
 ; RV64ZBS-NEXT:    andi a0, a0, 1
@@ -379,14 +379,14 @@ define signext i32 @sbext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
   ret i32 %and1
 }
 
-define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: sbext_i64:
+define i64 @bext_i64(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: bext_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbext_i64:
+; RV64ZBS-LABEL: bext_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bext a0, a0, a1
 ; RV64ZBS-NEXT:    ret
@@ -396,14 +396,14 @@ define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
   ret i64 %and1
 }
 
-define i64 @sbext_i64_no_mask(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: sbext_i64_no_mask:
+define i64 @bext_i64_no_mask(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: bext_i64_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbext_i64_no_mask:
+; RV64ZBS-LABEL: bext_i64_no_mask:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bext a0, a0, a1
 ; RV64ZBS-NEXT:    ret
@@ -412,14 +412,14 @@ define i64 @sbext_i64_no_mask(i64 %a, i64 %b) nounwind {
   ret i64 %and1
 }
 
-define signext i32 @sbexti_i32(i32 signext %a) nounwind {
-; RV64I-LABEL: sbexti_i32:
+define signext i32 @bexti_i32(i32 signext %a) nounwind {
+; RV64I-LABEL: bexti_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a0, a0, 5
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbexti_i32:
+; RV64ZBS-LABEL: bexti_i32:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bexti a0, a0, 5
 ; RV64ZBS-NEXT:    ret
@@ -428,14 +428,14 @@ define signext i32 @sbexti_i32(i32 signext %a) nounwind {
   ret i32 %and
 }
 
-define i64 @sbexti_i64(i64 %a) nounwind {
-; RV64I-LABEL: sbexti_i64:
+define i64 @bexti_i64(i64 %a) nounwind {
+; RV64I-LABEL: bexti_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a0, a0, 5
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbexti_i64:
+; RV64ZBS-LABEL: bexti_i64:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bexti a0, a0, 5
 ; RV64ZBS-NEXT:    ret
@@ -444,13 +444,13 @@ define i64 @sbexti_i64(i64 %a) nounwind {
   ret i64 %and
 }
 
-define signext i32 @sbclri_i32_10(i32 signext %a) nounwind {
-; RV64I-LABEL: sbclri_i32_10:
+define signext i32 @bclri_i32_10(i32 signext %a) nounwind {
+; RV64I-LABEL: bclri_i32_10:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    andi a0, a0, -1025
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i32_10:
+; RV64ZBS-LABEL: bclri_i32_10:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    andi a0, a0, -1025
 ; RV64ZBS-NEXT:    ret
@@ -458,15 +458,15 @@ define signext i32 @sbclri_i32_10(i32 signext %a) nounwind {
   ret i32 %and
 }
 
-define signext i32 @sbclri_i32_11(i32 signext %a) nounwind {
-; RV64I-LABEL: sbclri_i32_11:
+define signext i32 @bclri_i32_11(i32 signext %a) nounwind {
+; RV64I-LABEL: bclri_i32_11:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1048575
 ; RV64I-NEXT:    addiw a1, a1, 2047
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i32_11:
+; RV64ZBS-LABEL: bclri_i32_11:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclri a0, a0, 11
 ; RV64ZBS-NEXT:    ret
@@ -474,15 +474,15 @@ define signext i32 @sbclri_i32_11(i32 signext %a) nounwind {
   ret i32 %and
 }
 
-define signext i32 @sbclri_i32_30(i32 signext %a) nounwind {
-; RV64I-LABEL: sbclri_i32_30:
+define signext i32 @bclri_i32_30(i32 signext %a) nounwind {
+; RV64I-LABEL: bclri_i32_30:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 786432
 ; RV64I-NEXT:    addiw a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i32_30:
+; RV64ZBS-LABEL: bclri_i32_30:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclri a0, a0, 30
 ; RV64ZBS-NEXT:    ret
@@ -490,15 +490,15 @@ define signext i32 @sbclri_i32_30(i32 signext %a) nounwind {
   ret i32 %and
 }
 
-define signext i32 @sbclri_i32_31(i32 signext %a) nounwind {
-; RV64I-LABEL: sbclri_i32_31:
+define signext i32 @bclri_i32_31(i32 signext %a) nounwind {
+; RV64I-LABEL: bclri_i32_31:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    addiw a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i32_31:
+; RV64ZBS-LABEL: bclri_i32_31:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lui a1, 524288
 ; RV64ZBS-NEXT:    addiw a1, a1, -1
@@ -508,13 +508,13 @@ define signext i32 @sbclri_i32_31(i32 signext %a) nounwind {
   ret i32 %and
 }
 
-define i64 @sbclri_i64_10(i64 %a) nounwind {
-; RV64I-LABEL: sbclri_i64_10:
+define i64 @bclri_i64_10(i64 %a) nounwind {
+; RV64I-LABEL: bclri_i64_10:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    andi a0, a0, -1025
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i64_10:
+; RV64ZBS-LABEL: bclri_i64_10:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    andi a0, a0, -1025
 ; RV64ZBS-NEXT:    ret
@@ -522,15 +522,15 @@ define i64 @sbclri_i64_10(i64 %a) nounwind {
   ret i64 %and
 }
 
-define i64 @sbclri_i64_11(i64 %a) nounwind {
-; RV64I-LABEL: sbclri_i64_11:
+define i64 @bclri_i64_11(i64 %a) nounwind {
+; RV64I-LABEL: bclri_i64_11:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1048575
 ; RV64I-NEXT:    addiw a1, a1, 2047
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i64_11:
+; RV64ZBS-LABEL: bclri_i64_11:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclri a0, a0, 11
 ; RV64ZBS-NEXT:    ret
@@ -538,15 +538,15 @@ define i64 @sbclri_i64_11(i64 %a) nounwind {
   ret i64 %and
 }
 
-define i64 @sbclri_i64_30(i64 %a) nounwind {
-; RV64I-LABEL: sbclri_i64_30:
+define i64 @bclri_i64_30(i64 %a) nounwind {
+; RV64I-LABEL: bclri_i64_30:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 786432
 ; RV64I-NEXT:    addiw a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i64_30:
+; RV64ZBS-LABEL: bclri_i64_30:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclri a0, a0, 30
 ; RV64ZBS-NEXT:    ret
@@ -554,8 +554,8 @@ define i64 @sbclri_i64_30(i64 %a) nounwind {
   ret i64 %and
 }
 
-define i64 @sbclri_i64_31(i64 %a) nounwind {
-; RV64I-LABEL: sbclri_i64_31:
+define i64 @bclri_i64_31(i64 %a) nounwind {
+; RV64I-LABEL: bclri_i64_31:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, -1
 ; RV64I-NEXT:    slli a1, a1, 31
@@ -563,7 +563,7 @@ define i64 @sbclri_i64_31(i64 %a) nounwind {
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i64_31:
+; RV64ZBS-LABEL: bclri_i64_31:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclri a0, a0, 31
 ; RV64ZBS-NEXT:    ret
@@ -571,8 +571,8 @@ define i64 @sbclri_i64_31(i64 %a) nounwind {
   ret i64 %and
 }
 
-define i64 @sbclri_i64_62(i64 %a) nounwind {
-; RV64I-LABEL: sbclri_i64_62:
+define i64 @bclri_i64_62(i64 %a) nounwind {
+; RV64I-LABEL: bclri_i64_62:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, -1
 ; RV64I-NEXT:    slli a1, a1, 62
@@ -580,7 +580,7 @@ define i64 @sbclri_i64_62(i64 %a) nounwind {
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i64_62:
+; RV64ZBS-LABEL: bclri_i64_62:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclri a0, a0, 62
 ; RV64ZBS-NEXT:    ret
@@ -588,15 +588,15 @@ define i64 @sbclri_i64_62(i64 %a) nounwind {
   ret i64 %and
 }
 
-define i64 @sbclri_i64_63(i64 %a) nounwind {
-; RV64I-LABEL: sbclri_i64_63:
+define i64 @bclri_i64_63(i64 %a) nounwind {
+; RV64I-LABEL: bclri_i64_63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, -1
 ; RV64I-NEXT:    srli a1, a1, 1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i64_63:
+; RV64ZBS-LABEL: bclri_i64_63:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclri a0, a0, 63
 ; RV64ZBS-NEXT:    ret
@@ -604,15 +604,15 @@ define i64 @sbclri_i64_63(i64 %a) nounwind {
   ret i64 %and
 }
 
-define i64 @sbclri_i64_large0(i64 %a) nounwind {
-; RV64I-LABEL: sbclri_i64_large0:
+define i64 @bclri_i64_large0(i64 %a) nounwind {
+; RV64I-LABEL: bclri_i64_large0:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1044480
 ; RV64I-NEXT:    addiw a1, a1, -256
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i64_large0:
+; RV64ZBS-LABEL: bclri_i64_large0:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    andi a0, a0, -256
 ; RV64ZBS-NEXT:    bclri a0, a0, 24
@@ -621,15 +621,15 @@ define i64 @sbclri_i64_large0(i64 %a) nounwind {
   ret i64 %and
 }
 
-define i64 @sbclri_i64_large1(i64 %a) nounwind {
-; RV64I-LABEL: sbclri_i64_large1:
+define i64 @bclri_i64_large1(i64 %a) nounwind {
+; RV64I-LABEL: bclri_i64_large1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1044464
 ; RV64I-NEXT:    addiw a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbclri_i64_large1:
+; RV64ZBS-LABEL: bclri_i64_large1:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclri a0, a0, 16
 ; RV64ZBS-NEXT:    bclri a0, a0, 24
@@ -638,13 +638,13 @@ define i64 @sbclri_i64_large1(i64 %a) nounwind {
   ret i64 %and
 }
 
-define signext i32 @sbseti_i32_10(i32 signext %a) nounwind {
-; RV64I-LABEL: sbseti_i32_10:
+define signext i32 @bseti_i32_10(i32 signext %a) nounwind {
+; RV64I-LABEL: bseti_i32_10:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ori a0, a0, 1024
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbseti_i32_10:
+; RV64ZBS-LABEL: bseti_i32_10:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    ori a0, a0, 1024
 ; RV64ZBS-NEXT:    ret
@@ -652,15 +652,15 @@ define signext i32 @sbseti_i32_10(i32 signext %a) nounwind {
   ret i32 %or
 }
 
-define signext i32 @sbseti_i32_11(i32 signext %a) nounwind {
-; RV64I-LABEL: sbseti_i32_11:
+define signext i32 @bseti_i32_11(i32 signext %a) nounwind {
+; RV64I-LABEL: bseti_i32_11:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, -2048
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbseti_i32_11:
+; RV64ZBS-LABEL: bseti_i32_11:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a0, a0, 11
 ; RV64ZBS-NEXT:    ret
@@ -668,14 +668,14 @@ define signext i32 @sbseti_i32_11(i32 signext %a) nounwind {
   ret i32 %or
 }
 
-define signext i32 @sbseti_i32_30(i32 signext %a) nounwind {
-; RV64I-LABEL: sbseti_i32_30:
+define signext i32 @bseti_i32_30(i32 signext %a) nounwind {
+; RV64I-LABEL: bseti_i32_30:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 262144
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbseti_i32_30:
+; RV64ZBS-LABEL: bseti_i32_30:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a0, a0, 30
 ; RV64ZBS-NEXT:    ret
@@ -683,14 +683,14 @@ define signext i32 @sbseti_i32_30(i32 signext %a) nounwind {
   ret i32 %or
 }
 
-define signext i32 @sbseti_i32_31(i32 signext %a) nounwind {
-; RV64I-LABEL: sbseti_i32_31:
+define signext i32 @bseti_i32_31(i32 signext %a) nounwind {
+; RV64I-LABEL: bseti_i32_31:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbseti_i32_31:
+; RV64ZBS-LABEL: bseti_i32_31:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lui a1, 524288
 ; RV64ZBS-NEXT:    or a0, a0, a1
@@ -699,13 +699,13 @@ define signext i32 @sbseti_i32_31(i32 signext %a) nounwind {
   ret i32 %or
 }
 
-define i64 @sbseti_i64_10(i64 %a) nounwind {
-; RV64I-LABEL: sbseti_i64_10:
+define i64 @bseti_i64_10(i64 %a) nounwind {
+; RV64I-LABEL: bseti_i64_10:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ori a0, a0, 1024
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbseti_i64_10:
+; RV64ZBS-LABEL: bseti_i64_10:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    ori a0, a0, 1024
 ; RV64ZBS-NEXT:    ret
@@ -713,15 +713,15 @@ define i64 @sbseti_i64_10(i64 %a) nounwind {
   ret i64 %or
 }
 
-define i64 @sbseti_i64_11(i64 %a) nounwind {
-; RV64I-LABEL: sbseti_i64_11:
+define i64 @bseti_i64_11(i64 %a) nounwind {
+; RV64I-LABEL: bseti_i64_11:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, -2048
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbseti_i64_11:
+; RV64ZBS-LABEL: bseti_i64_11:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a0, a0, 11
 ; RV64ZBS-NEXT:    ret
@@ -729,14 +729,14 @@ define i64 @sbseti_i64_11(i64 %a) nounwind {
   ret i64 %or
 }
 
-define i64 @sbseti_i64_30(i64 %a) nounwind {
-; RV64I-LABEL: sbseti_i64_30:
+define i64 @bseti_i64_30(i64 %a) nounwind {
+; RV64I-LABEL: bseti_i64_30:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 262144
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbseti_i64_30:
+; RV64ZBS-LABEL: bseti_i64_30:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a0, a0, 30
 ; RV64ZBS-NEXT:    ret
@@ -744,15 +744,15 @@ define i64 @sbseti_i64_30(i64 %a) nounwind {
   ret i64 %or
 }
 
-define i64 @sbseti_i64_31(i64 %a) nounwind {
-; RV64I-LABEL: sbseti_i64_31:
+define i64 @bseti_i64_31(i64 %a) nounwind {
+; RV64I-LABEL: bseti_i64_31:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, 1
 ; RV64I-NEXT:    slli a1, a1, 31
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbseti_i64_31:
+; RV64ZBS-LABEL: bseti_i64_31:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a0, a0, 31
 ; RV64ZBS-NEXT:    ret
@@ -760,15 +760,15 @@ define i64 @sbseti_i64_31(i64 %a) nounwind {
   ret i64 %or
 }
 
-define i64 @sbseti_i64_62(i64 %a) nounwind {
-; RV64I-LABEL: sbseti_i64_62:
+define i64 @bseti_i64_62(i64 %a) nounwind {
+; RV64I-LABEL: bseti_i64_62:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, 1
 ; RV64I-NEXT:    slli a1, a1, 62
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbseti_i64_62:
+; RV64ZBS-LABEL: bseti_i64_62:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a0, a0, 62
 ; RV64ZBS-NEXT:    ret
@@ -776,15 +776,15 @@ define i64 @sbseti_i64_62(i64 %a) nounwind {
   ret i64 %or
 }
 
-define i64 @sbseti_i64_63(i64 %a) nounwind {
-; RV64I-LABEL: sbseti_i64_63:
+define i64 @bseti_i64_63(i64 %a) nounwind {
+; RV64I-LABEL: bseti_i64_63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, -1
 ; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbseti_i64_63:
+; RV64ZBS-LABEL: bseti_i64_63:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a0, a0, 63
 ; RV64ZBS-NEXT:    ret
@@ -792,13 +792,13 @@ define i64 @sbseti_i64_63(i64 %a) nounwind {
   ret i64 %or
 }
 
-define signext i32 @sbinvi_i32_10(i32 signext %a) nounwind {
-; RV64I-LABEL: sbinvi_i32_10:
+define signext i32 @binvi_i32_10(i32 signext %a) nounwind {
+; RV64I-LABEL: binvi_i32_10:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    xori a0, a0, 1024
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinvi_i32_10:
+; RV64ZBS-LABEL: binvi_i32_10:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    xori a0, a0, 1024
 ; RV64ZBS-NEXT:    ret
@@ -806,15 +806,15 @@ define signext i32 @sbinvi_i32_10(i32 signext %a) nounwind {
   ret i32 %xor
 }
 
-define signext i32 @sbinvi_i32_11(i32 signext %a) nounwind {
-; RV64I-LABEL: sbinvi_i32_11:
+define signext i32 @binvi_i32_11(i32 signext %a) nounwind {
+; RV64I-LABEL: binvi_i32_11:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, -2048
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinvi_i32_11:
+; RV64ZBS-LABEL: binvi_i32_11:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binvi a0, a0, 11
 ; RV64ZBS-NEXT:    ret
@@ -822,14 +822,14 @@ define signext i32 @sbinvi_i32_11(i32 signext %a) nounwind {
   ret i32 %xor
 }
 
-define signext i32 @sbinvi_i32_30(i32 signext %a) nounwind {
-; RV64I-LABEL: sbinvi_i32_30:
+define signext i32 @binvi_i32_30(i32 signext %a) nounwind {
+; RV64I-LABEL: binvi_i32_30:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 262144
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinvi_i32_30:
+; RV64ZBS-LABEL: binvi_i32_30:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binvi a0, a0, 30
 ; RV64ZBS-NEXT:    ret
@@ -837,14 +837,14 @@ define signext i32 @sbinvi_i32_30(i32 signext %a) nounwind {
   ret i32 %xor
 }
 
-define signext i32 @sbinvi_i32_31(i32 signext %a) nounwind {
-; RV64I-LABEL: sbinvi_i32_31:
+define signext i32 @binvi_i32_31(i32 signext %a) nounwind {
+; RV64I-LABEL: binvi_i32_31:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinvi_i32_31:
+; RV64ZBS-LABEL: binvi_i32_31:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lui a1, 524288
 ; RV64ZBS-NEXT:    xor a0, a0, a1
@@ -853,13 +853,13 @@ define signext i32 @sbinvi_i32_31(i32 signext %a) nounwind {
   ret i32 %xor
 }
 
-define i64 @sbinvi_i64_10(i64 %a) nounwind {
-; RV64I-LABEL: sbinvi_i64_10:
+define i64 @binvi_i64_10(i64 %a) nounwind {
+; RV64I-LABEL: binvi_i64_10:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    xori a0, a0, 1024
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinvi_i64_10:
+; RV64ZBS-LABEL: binvi_i64_10:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    xori a0, a0, 1024
 ; RV64ZBS-NEXT:    ret
@@ -867,15 +867,15 @@ define i64 @sbinvi_i64_10(i64 %a) nounwind {
   ret i64 %xor
 }
 
-define i64 @sbinvi_i64_11(i64 %a) nounwind {
-; RV64I-LABEL: sbinvi_i64_11:
+define i64 @binvi_i64_11(i64 %a) nounwind {
+; RV64I-LABEL: binvi_i64_11:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, -2048
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinvi_i64_11:
+; RV64ZBS-LABEL: binvi_i64_11:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binvi a0, a0, 11
 ; RV64ZBS-NEXT:    ret
@@ -883,14 +883,14 @@ define i64 @sbinvi_i64_11(i64 %a) nounwind {
   ret i64 %xor
 }
 
-define i64 @sbinvi_i64_30(i64 %a) nounwind {
-; RV64I-LABEL: sbinvi_i64_30:
+define i64 @binvi_i64_30(i64 %a) nounwind {
+; RV64I-LABEL: binvi_i64_30:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 262144
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinvi_i64_30:
+; RV64ZBS-LABEL: binvi_i64_30:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binvi a0, a0, 30
 ; RV64ZBS-NEXT:    ret
@@ -898,15 +898,15 @@ define i64 @sbinvi_i64_30(i64 %a) nounwind {
   ret i64 %xor
 }
 
-define i64 @sbinvi_i64_31(i64 %a) nounwind {
-; RV64I-LABEL: sbinvi_i64_31:
+define i64 @binvi_i64_31(i64 %a) nounwind {
+; RV64I-LABEL: binvi_i64_31:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, 1
 ; RV64I-NEXT:    slli a1, a1, 31
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinvi_i64_31:
+; RV64ZBS-LABEL: binvi_i64_31:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binvi a0, a0, 31
 ; RV64ZBS-NEXT:    ret
@@ -914,15 +914,15 @@ define i64 @sbinvi_i64_31(i64 %a) nounwind {
   ret i64 %xor
 }
 
-define i64 @sbinvi_i64_62(i64 %a) nounwind {
-; RV64I-LABEL: sbinvi_i64_62:
+define i64 @binvi_i64_62(i64 %a) nounwind {
+; RV64I-LABEL: binvi_i64_62:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, 1
 ; RV64I-NEXT:    slli a1, a1, 62
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinvi_i64_62:
+; RV64ZBS-LABEL: binvi_i64_62:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binvi a0, a0, 62
 ; RV64ZBS-NEXT:    ret
@@ -930,15 +930,15 @@ define i64 @sbinvi_i64_62(i64 %a) nounwind {
   ret i64 %xor
 }
 
-define i64 @sbinvi_i64_63(i64 %a) nounwind {
-; RV64I-LABEL: sbinvi_i64_63:
+define i64 @binvi_i64_63(i64 %a) nounwind {
+; RV64I-LABEL: binvi_i64_63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, -1
 ; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBS-LABEL: sbinvi_i64_63:
+; RV64ZBS-LABEL: binvi_i64_63:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binvi a0, a0, 63
 ; RV64ZBS-NEXT:    ret


        


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