[PATCH] D108115: [DAG][sve] Lowering for VLS masked truncating stores

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:10109
+    auto Mask = DAG.getNode(
+        ISD::SIGN_EXTEND, SDLoc(N),
+        getSetCCResultType(Value.getOperand(0).getValueType()), MST->getMask());
----------------
You'll need to follow the same idiom as `DAGTypeLegalizer::PromoteTargetBoolean` because although `ISD::SIGN_EXTEND` is correct for AArch64, other target's might need something else.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108115/new/

https://reviews.llvm.org/D108115