[PATCH] D115629: [RISCV] Use binvi and bexti to fold and (not (srl X, C)), 1
Jianjian Guan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 14 23:11:01 PST 2021
jacquesguan added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:795
+def : Pat<(and (not (srl GPR:$rs1, uimmlog2xlen:$shamt)), (XLenVT 1)),
+ (BEXTI (BINVI GPR:$rs1, uimmlog2xlen:$shamt),
+ uimmlog2xlen:$shamt)>;
----------------
jacquesguan wrote:
> craig.topper wrote:
> > I wonder if the (XORI (BEXTI GPR:$rs1, $shamt), 1) we would have gotten from the original InstCombine canonicalization would be better.
> >
> > Guess it depends on whether the Zbs instructions are implemented as well as XORI or not. There is no c.xori or that would have been a good reason to favor xori.
> Thanks, so that I could change DAGCombine to keep ` xor (and(srl X, C),1), 1` when we have single-Bit extract instruction in backend. In this situation, at least, we fold `(and(srl X, C),1)` into `BEXTI X, C`. What's your option about this?
Sorry, I misunderstanded your comment. Please ignore my last reply. I would simply change that pattern into
```def : Pat<(and (not (srl GPR:$rs1, uimmlog2xlen:$shamt)), (XLenVT 1)),
(XORI (BEXTI GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1))
```
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D115629/new/
https://reviews.llvm.org/D115629
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