[PATCH] D115435: [AArch64] Add a tablegen pattern for UZP1.

Tue Dec 14 02:00:08 PST 2021

dmgreen added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:5291

+def : Pat<(v4i32 (concat_vectors (v2i32 (trunc (v2i64 V128:$Vn))),
+                                 (v2i32 (trunc (v2i64 V128:$Vm))))),
----------------
labrinea wrote:
> dmgreen wrote:
> > SjoerdMeijer wrote:
> > > I was wondering if we also need patterns that work on V64 values/regs, so that we get the `uzp1 .8b` variants?
> > Does this pattern and the one below work? I think illegal types don't get this far through lowering, and tablegen often balks at them.
> Yes they do. I have added tests for them in `llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll`. However, the pattern for the `2s` variant didn't work (v1i64 --> v2i32).
OK. These two already seem to produce the single instruction, without the need for this patch:
https://godbolt.org/z/15Yh1a4bv

I'm not sure if they are actually doing much.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115435/new/

https://reviews.llvm.org/D115435