[PATCH] D115457: [AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0)

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:4815
 defm CMLE   : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
 defm CMLT   : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
 defm FCMEQ  : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
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labrinea wrote:
> dmgreen wrote:
> > There is a v1i64 CMLT here if you want to add the pattern for that too. v1 types usually matter less but it may be good to have it for consistency.
> There is no `1D` variant if that's what you meant. According to ArmARM the encoding (size = 11 , Q = 0) is reserved.
This is the "Scalar" variant, not the "Vector" variant.

This one, I think: https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Scalar-Instructions/CMLT--scalar--zero-


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  https://reviews.llvm.org/D115457/new/

https://reviews.llvm.org/D115457