[PATCH] D115435: [AArch64] Add a tablegen pattern for UZP1.

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:5291
 
+def : Pat<(v4i32 (concat_vectors (v2i32 (trunc (v2i64 V128:$Vn))),
+                                 (v2i32 (trunc (v2i64 V128:$Vm))))),
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SjoerdMeijer wrote:
> I was wondering if we also need patterns that work on V64 values/regs, so that we get the `uzp1 .8b` variants?
Does this pattern and the one below work? I think illegal types don't get this far through lowering, and tablegen often balks at them.


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  https://reviews.llvm.org/D115435/new/

https://reviews.llvm.org/D115435