[llvm] 10a7198 - [RISCV] Support named opcodes in .insn directive.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 13 21:15:44 PST 2021
Author: Nelson Chu
Date: 2021-12-13T20:59:33-08:00
New Revision: 10a71981e92d24bf7f93ed21b2acfc2e04c00472
URL: https://github.com/llvm/llvm-project/commit/10a71981e92d24bf7f93ed21b2acfc2e04c00472
DIFF: https://github.com/llvm/llvm-project/commit/10a71981e92d24bf7f93ed21b2acfc2e04c00472.diff
LOG: [RISCV] Support named opcodes in .insn directive.
This patch is one of the TODO of commit, 283879793dc787225992496587581ec77b6b0610
We build the GenericTable for these opcodes, and also extend class RISCVOpcode, to store the names of opcodes. Then we call the parseInsnDirectiveOpcode to parse the opcode filed in .insn directive. We only allow users to write the recognized opcode names, or just write the immediate values in the 7 bits range.
Documentation: https://sourceware.org/binutils/docs-2.37/as/RISC_002dV_002dFormats.html
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D115224
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/MC/RISCV/insn-invalid.s
llvm/test/MC/RISCV/insn.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 6cc0e1f3e5a57..75592dd4c6f54 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -169,6 +169,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
OperandMatchResultTy parseJALOffset(OperandVector &Operands);
OperandMatchResultTy parseVTypeI(OperandVector &Operands);
OperandMatchResultTy parseMaskReg(OperandVector &Operands);
+ OperandMatchResultTy parseInsnDirectiveOpcode(OperandVector &Operands);
bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
@@ -1306,6 +1307,67 @@ OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands,
return MatchOperand_Success;
}
+OperandMatchResultTy
+RISCVAsmParser::parseInsnDirectiveOpcode(OperandVector &Operands) {
+ SMLoc S = getLoc();
+ SMLoc E;
+ const MCExpr *Res;
+
+ switch (getLexer().getKind()) {
+ default:
+ return MatchOperand_NoMatch;
+ case AsmToken::LParen:
+ case AsmToken::Minus:
+ case AsmToken::Plus:
+ case AsmToken::Exclaim:
+ case AsmToken::Tilde:
+ case AsmToken::Integer:
+ case AsmToken::String: {
+ if (getParser().parseExpression(Res, E))
+ return MatchOperand_ParseFail;
+
+ auto *CE = dyn_cast<MCConstantExpr>(Res);
+ if (CE) {
+ int64_t Imm = CE->getValue();
+ if (isUInt<7>(Imm)) {
+ Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
+ return MatchOperand_Success;
+ }
+ }
+
+ Twine Msg = "immediate must be an integer in the range";
+ Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 7) - 1) + "]");
+ return MatchOperand_ParseFail;
+ }
+ case AsmToken::Identifier: {
+ StringRef Identifier;
+ if (getParser().parseIdentifier(Identifier))
+ return MatchOperand_ParseFail;
+
+ auto Opcode = RISCVInsnOpcode::lookupRISCVOpcodeByName(Identifier);
+ if (Opcode) {
+ Res = MCConstantExpr::create(Opcode->Value, getContext());
+ E = SMLoc::getFromPointer(S.getPointer() + Identifier.size());
+ Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
+ return MatchOperand_Success;
+ }
+
+ Twine Msg = "operand must be a valid opcode name or an "
+ "integer in the range";
+ Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 7) - 1) + "]");
+ return MatchOperand_ParseFail;
+ }
+ case AsmToken::Percent: {
+ // Discard operand with modifier.
+ Twine Msg = "immediate must be an integer in the range";
+ Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 7) - 1) + "]");
+ return MatchOperand_ParseFail;
+ }
+ }
+
+ return MatchOperand_NoMatch;
+}
+
OperandMatchResultTy
RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) {
SMLoc S = getLoc();
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index 0aba18b20f0da..144e761f002dc 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -27,6 +27,11 @@ namespace RISCVSysReg {
#include "RISCVGenSearchableTables.inc"
} // namespace RISCVSysReg
+namespace RISCVInsnOpcode {
+#define GET_RISCVOpcodesList_IMPL
+#include "RISCVGenSearchableTables.inc"
+} // namespace RISCVInsnOpcode
+
namespace RISCVABI {
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
StringRef ABIName) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index d8f4403c824f4..9cfd36745f46f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -299,6 +299,16 @@ struct SysReg {
#include "RISCVGenSearchableTables.inc"
} // end namespace RISCVSysReg
+namespace RISCVInsnOpcode {
+struct RISCVOpcode {
+ const char *Name;
+ unsigned Value;
+};
+
+#define GET_RISCVOpcodesList_DECL
+#include "RISCVGenSearchableTables.inc"
+} // end namespace RISCVInsnOpcode
+
namespace RISCVABI {
enum ABI {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index d28d41a989cf3..1bebf7b75a25b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -107,31 +107,44 @@ def Vcompress : RISCVVConstraint<!or(VS2Constraint.Value,
// The following opcode names match those given in Table 19.1 in the
// RISC-V User-level ISA specification ("RISC-V base opcode map").
-class RISCVOpcode<bits<7> val> {
+class RISCVOpcode<string name, bits<7> val> {
+ string Name = name;
bits<7> Value = val;
}
-def OPC_LOAD : RISCVOpcode<0b0000011>;
-def OPC_LOAD_FP : RISCVOpcode<0b0000111>;
-def OPC_MISC_MEM : RISCVOpcode<0b0001111>;
-def OPC_OP_IMM : RISCVOpcode<0b0010011>;
-def OPC_AUIPC : RISCVOpcode<0b0010111>;
-def OPC_OP_IMM_32 : RISCVOpcode<0b0011011>;
-def OPC_STORE : RISCVOpcode<0b0100011>;
-def OPC_STORE_FP : RISCVOpcode<0b0100111>;
-def OPC_AMO : RISCVOpcode<0b0101111>;
-def OPC_OP : RISCVOpcode<0b0110011>;
-def OPC_LUI : RISCVOpcode<0b0110111>;
-def OPC_OP_32 : RISCVOpcode<0b0111011>;
-def OPC_MADD : RISCVOpcode<0b1000011>;
-def OPC_MSUB : RISCVOpcode<0b1000111>;
-def OPC_NMSUB : RISCVOpcode<0b1001011>;
-def OPC_NMADD : RISCVOpcode<0b1001111>;
-def OPC_OP_FP : RISCVOpcode<0b1010011>;
-def OPC_OP_V : RISCVOpcode<0b1010111>;
-def OPC_BRANCH : RISCVOpcode<0b1100011>;
-def OPC_JALR : RISCVOpcode<0b1100111>;
-def OPC_JAL : RISCVOpcode<0b1101111>;
-def OPC_SYSTEM : RISCVOpcode<0b1110011>;
+def RISCVOpcodesList : GenericTable {
+ let FilterClass = "RISCVOpcode";
+ let Fields = [
+ "Name", "Value"
+ ];
+ let PrimaryKey = [ "Value" ];
+ let PrimaryKeyName = "lookupRISCVOpcodeByValue";
+}
+def lookupRISCVOpcodeByName : SearchIndex {
+ let Table = RISCVOpcodesList;
+ let Key = [ "Name" ];
+}
+def OPC_LOAD : RISCVOpcode<"LOAD", 0b0000011>;
+def OPC_LOAD_FP : RISCVOpcode<"LOAD_FP", 0b0000111>;
+def OPC_MISC_MEM : RISCVOpcode<"MISC_MEM", 0b0001111>;
+def OPC_OP_IMM : RISCVOpcode<"OP_IMM", 0b0010011>;
+def OPC_AUIPC : RISCVOpcode<"AUIPC", 0b0010111>;
+def OPC_OP_IMM_32 : RISCVOpcode<"OP_IMM_32", 0b0011011>;
+def OPC_STORE : RISCVOpcode<"STORE", 0b0100011>;
+def OPC_STORE_FP : RISCVOpcode<"STORE_FP", 0b0100111>;
+def OPC_AMO : RISCVOpcode<"AMO", 0b0101111>;
+def OPC_OP : RISCVOpcode<"OP", 0b0110011>;
+def OPC_LUI : RISCVOpcode<"LUI", 0b0110111>;
+def OPC_OP_32 : RISCVOpcode<"OP_32", 0b0111011>;
+def OPC_MADD : RISCVOpcode<"MADD", 0b1000011>;
+def OPC_MSUB : RISCVOpcode<"MSUB", 0b1000111>;
+def OPC_NMSUB : RISCVOpcode<"NMSUB", 0b1001011>;
+def OPC_NMADD : RISCVOpcode<"NMADD", 0b1001111>;
+def OPC_OP_FP : RISCVOpcode<"OP_FP", 0b1010011>;
+def OPC_OP_V : RISCVOpcode<"OP_V", 0b1010111>;
+def OPC_BRANCH : RISCVOpcode<"BRANCH", 0b1100011>;
+def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>;
+def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>;
+def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>;
class RVInst<dag outs, dag ins, string opcodestr, string argstr,
list<dag> pattern, InstFormat format>
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 6f9cde9661325..71eb6f01a4f42 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -174,6 +174,20 @@ def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
let OperandNamespace = "RISCVOp";
}
+def InsnDirectiveOpcode : AsmOperandClass {
+ let Name = "InsnDirectiveOpcode";
+ let ParserMethod = "parseInsnDirectiveOpcode";
+ let RenderMethod = "addImmOperands";
+ let PredicateMethod = "isImm";
+}
+
+def uimm7_opcode : Operand<XLenVT> {
+ let ParserMatchClass = InsnDirectiveOpcode;
+ let DecoderMethod = "decodeUImmOperand<7>";
+ let OperandType = "OPERAND_UIMM7";
+ let OperandNamespace = "RISCVOp";
+}
+
def uimm7 : Operand<XLenVT> {
let ParserMatchClass = UImmAsmOperand<7>;
let DecoderMethod = "decodeUImmOperand<7>";
@@ -878,35 +892,35 @@ def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>;
// isCodeGenOnly = 1 to hide them from the tablegened assembly parser.
let isCodeGenOnly = 1, hasSideEffects = 1, mayLoad = 1, mayStore = 1,
hasNoSchedulingInfo = 1 in {
-def InsnR : DirectiveInsnR<(outs AnyReg:$rd), (ins uimm7:$opcode, uimm3:$funct3,
+def InsnR : DirectiveInsnR<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode, uimm3:$funct3,
uimm7:$funct7, AnyReg:$rs1,
AnyReg:$rs2),
"$opcode, $funct3, $funct7, $rd, $rs1, $rs2">;
-def InsnR4 : DirectiveInsnR4<(outs AnyReg:$rd), (ins uimm7:$opcode,
+def InsnR4 : DirectiveInsnR4<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
uimm3:$funct3,
uimm2:$funct2,
AnyReg:$rs1, AnyReg:$rs2,
AnyReg:$rs3),
"$opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3">;
-def InsnI : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7:$opcode, uimm3:$funct3,
+def InsnI : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode, uimm3:$funct3,
AnyReg:$rs1, simm12:$imm12),
"$opcode, $funct3, $rd, $rs1, $imm12">;
-def InsnI_Mem : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7:$opcode,
+def InsnI_Mem : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
uimm3:$funct3,
AnyReg:$rs1,
simm12:$imm12),
"$opcode, $funct3, $rd, ${imm12}(${rs1})">;
-def InsnB : DirectiveInsnB<(outs), (ins uimm7:$opcode, uimm3:$funct3,
+def InsnB : DirectiveInsnB<(outs), (ins uimm7_opcode:$opcode, uimm3:$funct3,
AnyReg:$rs1, AnyReg:$rs2,
simm13_lsb0:$imm12),
"$opcode, $funct3, $rs1, $rs2, $imm12">;
-def InsnU : DirectiveInsnU<(outs AnyReg:$rd), (ins uimm7:$opcode,
+def InsnU : DirectiveInsnU<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
uimm20_lui:$imm20),
"$opcode, $rd, $imm20">;
-def InsnJ : DirectiveInsnJ<(outs AnyReg:$rd), (ins uimm7:$opcode,
+def InsnJ : DirectiveInsnJ<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
simm21_lsb0_jal:$imm20),
"$opcode, $rd, $imm20">;
-def InsnS : DirectiveInsnS<(outs), (ins uimm7:$opcode, uimm3:$funct3,
+def InsnS : DirectiveInsnS<(outs), (ins uimm7_opcode:$opcode, uimm3:$funct3,
AnyReg:$rs2, AnyReg:$rs1,
simm12:$imm12),
"$opcode, $funct3, $rs2, ${imm12}(${rs1})">;
@@ -918,37 +932,37 @@ def InsnS : DirectiveInsnS<(outs), (ins uimm7:$opcode, uimm3:$funct3,
// for known formats.
let EmitPriority = 0 in {
def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2",
- (InsnR AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7,
+ (InsnR AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, uimm7:$funct7,
AnyReg:$rs1, AnyReg:$rs2)>;
// Accept 4 register form of ".insn r" as alias for ".insn r4".
def : InstAlias<".insn_r $opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3",
- (InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm2:$funct2,
+ (InsnR4 AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, uimm2:$funct2,
AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>;
def : InstAlias<".insn_r4 $opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3",
- (InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm2:$funct2,
+ (InsnR4 AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, uimm2:$funct2,
AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>;
def : InstAlias<".insn_i $opcode, $funct3, $rd, $rs1, $imm12",
- (InsnI AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1,
+ (InsnI AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1,
simm12:$imm12)>;
def : InstAlias<".insn_i $opcode, $funct3, $rd, ${imm12}(${rs1})",
- (InsnI_Mem AnyReg:$rd, uimm7:$opcode, uimm3:$funct3,
+ (InsnI_Mem AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3,
AnyReg:$rs1, simm12:$imm12)>;
def : InstAlias<".insn_b $opcode, $funct3, $rs1, $rs2, $imm12",
- (InsnB uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1,
+ (InsnB uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1,
AnyReg:$rs2, simm13_lsb0:$imm12)>;
// Accept sb as an alias for b.
def : InstAlias<".insn_sb $opcode, $funct3, $rs1, $rs2, $imm12",
- (InsnB uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1,
+ (InsnB uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1,
AnyReg:$rs2, simm13_lsb0:$imm12)>;
def : InstAlias<".insn_u $opcode, $rd, $imm20",
- (InsnU AnyReg:$rd, uimm7:$opcode, uimm20_lui:$imm20)>;
+ (InsnU AnyReg:$rd, uimm7_opcode:$opcode, uimm20_lui:$imm20)>;
def : InstAlias<".insn_j $opcode, $rd, $imm20",
- (InsnJ AnyReg:$rd, uimm7:$opcode, simm21_lsb0_jal:$imm20)>;
+ (InsnJ AnyReg:$rd, uimm7_opcode:$opcode, simm21_lsb0_jal:$imm20)>;
// Accept uj as an alias for j.
def : InstAlias<".insn_uj $opcode, $rd, $imm20",
- (InsnJ AnyReg:$rd, uimm7:$opcode, simm21_lsb0_jal:$imm20)>;
+ (InsnJ AnyReg:$rd, uimm7_opcode:$opcode, simm21_lsb0_jal:$imm20)>;
def : InstAlias<".insn_s $opcode, $funct3, $rs2, ${imm12}(${rs1})",
- (InsnS uimm7:$opcode, uimm3:$funct3, AnyReg:$rs2,
+ (InsnS uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs2,
AnyReg:$rs1, simm12:$imm12)>;
}
diff --git a/llvm/test/MC/RISCV/insn-invalid.s b/llvm/test/MC/RISCV/insn-invalid.s
index 39f77ef1d0b24..c9142747f07db 100644
--- a/llvm/test/MC/RISCV/insn-invalid.s
+++ b/llvm/test/MC/RISCV/insn-invalid.s
@@ -18,5 +18,8 @@
.insn r 0x33, 8, 0, a0, a1, a2 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7]
.insn r4 0x43, 0, 4, fa0, fa1, fa2, fa3 # CHECK: :[[@LINE]]:21: error: immediate must be an integer in the range [0, 3]
+# Unrecognized opcode name
+.insn r UNKNOWN, 0, a1, a2, a3 #CHECK: :[[@LINE]]:9: error: operand must be a valid opcode name or an integer in the range [0, 127]
+
# Make fake mnemonics we use to match these in the tablegened asm match table isn't exposed.
.insn_i 0x13, 0, a0, a1, 13, 14 # CHECK: :[[@LINE]]:1: error: unknown directive
diff --git a/llvm/test/MC/RISCV/insn.s b/llvm/test/MC/RISCV/insn.s
index 1e02e22f965ad..158201e1cf7f4 100644
--- a/llvm/test/MC/RISCV/insn.s
+++ b/llvm/test/MC/RISCV/insn.s
@@ -15,63 +15,115 @@ target:
# CHECK-ASM: encoding: [0x33,0x85,0xc5,0x00]
# CHECK-OBJ: add a0, a1, a2
.insn r 0x33, 0, 0, a0, a1, a2
+# CHECK-ASM: .insn r 51, 0, 0, a0, a1, a2
+# CHECK-ASM: encoding: [0x33,0x85,0xc5,0x00]
+# CHECK-OBJ: add a0, a1, a2
+.insn r OP, 0, 0, a0, a1, a2
# CHECK-ASM: .insn i 19, 0, a0, a1, 13
# CHECK-ASM: encoding: [0x13,0x85,0xd5,0x00]
# CHECK-OBJ: addi a0, a1, 13
.insn i 0x13, 0, a0, a1, 13
+# CHECK-ASM: .insn i 19, 0, a0, a1, 13
+# CHECK-ASM: encoding: [0x13,0x85,0xd5,0x00]
+# CHECK-OBJ: addi a0, a1, 13
+.insn i OP_IMM, 0, a0, a1, 13
# CHECK-ASM: .insn i 103, 0, a0, 10(a1)
# CHECK-ASM: encoding: [0x67,0x85,0xa5,0x00]
# CHECK-OBJ: jalr a0, 10(a1)
.insn i 0x67, 0, a0, 10(a1)
+# CHECK-ASM: .insn i 103, 0, a0, 10(a1)
+# CHECK-ASM: encoding: [0x67,0x85,0xa5,0x00]
+# CHECK-OBJ: jalr a0, 10(a1)
+.insn i JALR, 0, a0, 10(a1)
# CHECK-ASM: .insn i 3, 0, a0, 4(a1)
# CHECK-ASM: encoding: [0x03,0x85,0x45,0x00]
# CHECK-OBJ: lb a0, 4(a1)
.insn i 0x3, 0, a0, 4(a1)
+# CHECK-ASM: .insn i 3, 0, a0, 4(a1)
+# CHECK-ASM: encoding: [0x03,0x85,0x45,0x00]
+# CHECK-OBJ: lb a0, 4(a1)
+.insn i LOAD, 0, a0, 4(a1)
# CHECK-ASM: .insn b 99, 0, a0, a1, target
# CHECK-ASM: [0x63'A',A,0xb5'A',A]
# CHECK-OBJ: beq a0, a1, 0x0 <target>
.insn sb 0x63, 0, a0, a1, target
+# CHECK-ASM: .insn b 99, 0, a0, a1, target
+# CHECK-ASM: [0x63'A',A,0xb5'A',A]
+# CHECK-OBJ: beq a0, a1, 0x0 <target>
+.insn sb BRANCH, 0, a0, a1, target
# CHECK-ASM: .insn b 99, 0, a0, a1, target
# CHECK-ASM: [0x63'A',A,0xb5'A',A]
# CHECK-OBJ: beq a0, a1, 0x0 <target>
.insn b 0x63, 0, a0, a1, target
+# CHECK-ASM: .insn b 99, 0, a0, a1, target
+# CHECK-ASM: [0x63'A',A,0xb5'A',A]
+# CHECK-OBJ: beq a0, a1, 0x0 <target>
+.insn b BRANCH, 0, a0, a1, target
# CHECK-ASM: .insn s 35, 0, a0, 4(a1)
# CHECK-ASM: encoding: [0x23,0x82,0xa5,0x00]
# CHECK-OBJ: sb a0, 4(a1)
.insn s 0x23, 0, a0, 4(a1)
+# CHECK-ASM: .insn s 35, 0, a0, 4(a1)
+# CHECK-ASM: encoding: [0x23,0x82,0xa5,0x00]
+# CHECK-OBJ: sb a0, 4(a1)
+.insn s STORE, 0, a0, 4(a1)
# CHECK-ASM: .insn u 55, a0, 4095
# CHECK-ASM: encoding: [0x37,0xf5,0xff,0x00]
# CHECK-OBJ: lui a0, 4095
.insn u 0x37, a0, 0xfff
+# CHECK-ASM: .insn u 55, a0, 4095
+# CHECK-ASM: encoding: [0x37,0xf5,0xff,0x00]
+# CHECK-OBJ: lui a0, 4095
+.insn u LUI, a0, 0xfff
# CHECK-ASM: .insn j 111, a0, target
# CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A]
# CHECK-OBJ: jal a0, 0x0 <target>
.insn uj 0x6f, a0, target
+# CHECK-ASM: .insn j 111, a0, target
+# CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A]
+# CHECK-OBJ: jal a0, 0x0 <target>
+.insn uj JAL, a0, target
# CHECK-ASM: .insn j 111, a0, target
# CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A]
# CHECK-OBJ: jal a0, 0x0 <target>
.insn j 0x6f, a0, target
+# CHECK-ASM: .insn j 111, a0, target
+# CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A]
+# CHECK-OBJ: jal a0, 0x0 <target>
+.insn j JAL, a0, target
# CHECK-ASM: .insn r4 67, 0, 0, fa0, fa1, fa2, fa3
# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68]
# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne
.insn r 0x43, 0, 0, fa0, fa1, fa2, fa3
+# CHECK-ASM: .insn r4 67, 0, 0, fa0, fa1, fa2, fa3
+# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68]
+# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne
+.insn r MADD, 0, 0, fa0, fa1, fa2, fa3
# CHECK-ASM: .insn r4 67, 0, 0, fa0, fa1, fa2, fa3
# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68]
# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne
.insn r4 0x43, 0, 0, fa0, fa1, fa2, fa3
+# CHECK-ASM: .insn r4 67, 0, 0, fa0, fa1, fa2, fa3
+# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68]
+# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne
+.insn r4 MADD, 0, 0, fa0, fa1, fa2, fa3
# CHECK-ASM: .insn i 3, 5, t1, -2048(t2)
# CHECK-ASM: encoding: [0x03,0xd3,0x03,0x80]
# CHECK-OBJ: lhu t1, -2048(t2)
.insn i 0x3, 0x5, x6, %lo(2048)(x7)
+# CHECK-ASM: .insn i 3, 5, t1, -2048(t2)
+# CHECK-ASM: encoding: [0x03,0xd3,0x03,0x80]
+# CHECK-OBJ: lhu t1, -2048(t2)
+.insn i LOAD, 0x5, x6, %lo(2048)(x7)
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