[PATCH] D115691: [PowerPC] Update P10 vector insert patterns to utilize the refactored load/store infrastructure.

[Amy Kwan via Phabricator via llvm-commits]

amyk created this revision.
amyk added reviewers: PowerPC, nemanjai.
amyk added projects: LLVM, PowerPC.
Herald added subscribers: shchenz, kbarton, hiraditya.
amyk requested review of this revision.

This patch updates the P10 <https://reviews.llvm.org/P10> patterns with a load feeding into an `insertelt` to utilize the
refactored load and store infrastructure, as well as updating any tests that exhibit any
codegen changes.

Additionally, a DAG combine is added to the pattern for a f32 load feeding into a
v4f32 `insertelt` in order to exploit the refactored load and store architecture correctly.
In this situation, a f32 load is converted into an i32 load which is then fed into a
v4i32 `insertelt` in order to finally be bitcasted into a v4f32 `insertelt`. As a result of
the DAG combine, the specific `(v4f32 (insertelt (f32 load))` pattern is no longer
needed, and is removed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115691

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll

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