[llvm] 2de9338 - [MIPS] Allow i1 values for 'r' constraint in inline-asm

Simon Atanasyan via llvm-commits llvm-commits at lists.llvm.org
Mon Dec 13 14:20:10 PST 2021


Author: Simon Atanasyan
Date: 2021-12-14T01:19:34+03:00
New Revision: 2de9338587ffbad3a3f6249a615ab6c9e003813e

URL: https://github.com/llvm/llvm-project/commit/2de9338587ffbad3a3f6249a615ab6c9e003813e
DIFF: https://github.com/llvm/llvm-project/commit/2de9338587ffbad3a3f6249a615ab6c9e003813e.diff

LOG: [MIPS] Allow i1 values for 'r' constraint in inline-asm

The bug was reported in the issue #52638.

Added: 
    llvm/test/CodeGen/Mips/inlineasm-constraint-r-i1.ll

Modified: 
    llvm/lib/Target/Mips/MipsISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 4f364ef6afc7a..9377e83524e17 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4121,7 +4121,7 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
     case 'y': // Same as 'r'. Exists for compatibility.
     case 'r':
-      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
+      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
         if (Subtarget.inMips16Mode())
           return std::make_pair(0U, &Mips::CPU16RegsRegClass);
         return std::make_pair(0U, &Mips::GPR32RegClass);

diff  --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-r-i1.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-r-i1.ll
new file mode 100644
index 0000000000000..134d565125596
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-r-i1.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=mips < %s | FileCheck %s
+
+ at a = global i8 0, align 1
+
+define void @b() {
+entry:
+  %0 = load i8, i8* @a, align 1
+  %tobool = trunc i8 %0 to i1
+  call void asm sideeffect "", "Jr,~{$1}"(i1 %tobool)
+  ret void
+}
+
+; CHECK:      lui $1, %hi(a)
+; CHECK-NEXT: lbu $2, %lo(a)($1)


        


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