[PATCH] D114856: [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/div-pow2.ll:14
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    srli a1, a0, 31
+; RV32I-NEXT:    add a0, a0, a1
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I think it makes sense to keep the old codegen when dividing by 2.


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Comment at: llvm/test/CodeGen/RISCV/div-pow2.ll:58
+; RV32ZBT:       # %bb.0: # %entry
+; RV32ZBT-NEXT:    slti a1, a0, 0
+; RV32ZBT-NEXT:    addi a2, a0, 1
----------------
Original code is less instructions and has the same critical path instruction count.


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Comment at: llvm/test/CodeGen/RISCV/div-pow2.ll:355
+; RV64ZBT:       # %bb.0: # %entry
+; RV64ZBT-NEXT:    slti a1, a0, 0
+; RV64ZBT-NEXT:    addi a2, a0, 1
----------------
Original code looks better.


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Comment at: llvm/test/CodeGen/RISCV/div-pow2.ll:406
+; RV64ZBT:       # %bb.0: # %entry
+; RV64ZBT-NEXT:    slti a1, a0, 0
+; RV64ZBT-NEXT:    addi a2, a0, 1
----------------
Original code looks better


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114856/new/

https://reviews.llvm.org/D114856