[llvm] 61f8af2 - [AMDGPU] Remove a FIXME implemented in D11061

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-12-13T14:46:40Z
New Revision: 61f8af265728013bc979253ac536e52b98210325

URL: https://github.com/llvm/llvm-project/commit/61f8af265728013bc979253ac536e52b98210325
DIFF: https://github.com/llvm/llvm-project/commit/61f8af265728013bc979253ac536e52b98210325.diff

LOG: [AMDGPU] Remove a FIXME implemented in D11061

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index bdc349c8c813..0a68aa63e4b5 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3656,12 +3656,6 @@ bool SIInstrInfo::canShrink(const MachineInstr &MI,
                             const MachineRegisterInfo &MRI) const {
   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
   // Can't shrink instruction with three operands.
-  // FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
-  // a special case for it.  It can only be shrunk if the third operand
-  // is vcc, and src0_modifiers and src1_modifiers are not set.
-  // We should handle this the same way we handle vopc, by addding
-  // a register allocation hint pre-regalloc and then do the shrinking
-  // post-regalloc.
   if (Src2) {
     switch (MI.getOpcode()) {
       default: return false;