[PATCH] D108115: [DAG][sve] Lowering for VLS masked truncating stores

Mon Dec 13 04:30:31 PST 2021

DavidTruby added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18161

+  if (Store->isTruncatingStore()) {
+    Mask = DAG.getNode(
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dmgreen wrote:
> dmgreen wrote:
> > Why do we need to extend the mask? So that convertFixedMaskToScalableVector shrinks to a i1 vector again?
> @paulwalker-arm do the aarch64 portions of this patch look OK to you? If so I think the rest of this patch is fine.
I think the reason we need to extend here is that fixed-length i1 vectors are not legal types, so the following function needs it to be a non-i1 vector to work correctly.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108115/new/

https://reviews.llvm.org/D108115