[PATCH] D115547: [X86] Adjust some IceLake integer shuffle schedule classes (PR48110)

Mon Dec 13 01:16:39 PST 2021

RKSimon added a comment.

In D115547#3188305 <https://reviews.llvm.org/D115547#3188305>, @HaohaiWen wrote:

> Here's diff I found: https://www.textcompare.org/?id=61b7080d8668ef0015be12a9
> Left window is before this patch, right is after.
> Seems like VPBROADCASTBZ128rm, VPCMOVYrmr, VPPERMrmr ports change from [5, 23] to [15, 23] but we didn't have list test for them.

Cheers - I'll get these added to the llvm-mca test coverage.

> BTW, uops.info provides lat/tpt for icelake, not icelake-server.

Are there actual known sched diffs for ICL/ICX/RKL/TGL? I hadn't noticed any in instlatx64 listings etc. All I know is TGL supports VP2INTERSECT but the others do not - I'll add that at some point (maybe like IvyBridge F16C which we added under SandyBridge llvm-mca tests).

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D115547/new/

https://reviews.llvm.org/D115547