[llvm] 0a08813 - [X86][MMX] Remove superfluous 'i' from MMX binop opnames. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 12 10:02:05 PST 2021
Author: Simon Pilgrim
Date: 2021-12-12T17:59:16Z
New Revision: 0a08813cadf1ed01cd67e44eba6c54a9d0cde93a
URL: https://github.com/llvm/llvm-project/commit/0a08813cadf1ed01cd67e44eba6c54a9d0cde93a
DIFF: https://github.com/llvm/llvm-project/commit/0a08813cadf1ed01cd67e44eba6c54a9d0cde93a.diff
LOG: [X86][MMX] Remove superfluous 'i' from MMX binop opnames. NFCI.
This is a very old copy+paste typo - none of these binops have an immediate operand.
Noticed while trying to merge MMX instructions into some existing SSE instruction scheduler instregex patterns.
Added:
Modified:
llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
llvm/lib/Target/X86/X86InstrFoldTables.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrMMX.td
llvm/lib/Target/X86/X86SchedBroadwell.td
llvm/lib/Target/X86/X86SchedHaswell.td
llvm/lib/Target/X86/X86SchedIceLake.td
llvm/lib/Target/X86/X86SchedSandyBridge.td
llvm/lib/Target/X86/X86SchedSkylakeClient.td
llvm/lib/Target/X86/X86SchedSkylakeServer.td
llvm/lib/Target/X86/X86ScheduleAtom.td
llvm/lib/Target/X86/X86ScheduleBdVer2.td
llvm/lib/Target/X86/X86ScheduleBtVer2.td
llvm/lib/Target/X86/X86ScheduleSLM.td
llvm/lib/Target/X86/X86ScheduleZnver1.td
llvm/lib/Target/X86/X86ScheduleZnver2.td
llvm/lib/Target/X86/X86ScheduleZnver3.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
index b51011e2c52fc..a903c5f455a2e 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
@@ -948,39 +948,39 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
break;
CASE_UNPCK(PUNPCKHBW, r)
- case X86::MMX_PUNPCKHBWirr:
+ case X86::MMX_PUNPCKHBWrr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKHBW, m)
- case X86::MMX_PUNPCKHBWirm:
+ case X86::MMX_PUNPCKHBWrm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
DecodeUNPCKHMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
break;
CASE_UNPCK(PUNPCKHWD, r)
- case X86::MMX_PUNPCKHWDirr:
+ case X86::MMX_PUNPCKHWDrr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKHWD, m)
- case X86::MMX_PUNPCKHWDirm:
+ case X86::MMX_PUNPCKHWDrm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
DecodeUNPCKHMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
break;
CASE_UNPCK(PUNPCKHDQ, r)
- case X86::MMX_PUNPCKHDQirr:
+ case X86::MMX_PUNPCKHDQrr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKHDQ, m)
- case X86::MMX_PUNPCKHDQirm:
+ case X86::MMX_PUNPCKHDQrm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
@@ -998,39 +998,39 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
break;
CASE_UNPCK(PUNPCKLBW, r)
- case X86::MMX_PUNPCKLBWirr:
+ case X86::MMX_PUNPCKLBWrr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKLBW, m)
- case X86::MMX_PUNPCKLBWirm:
+ case X86::MMX_PUNPCKLBWrm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
DecodeUNPCKLMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
break;
CASE_UNPCK(PUNPCKLWD, r)
- case X86::MMX_PUNPCKLWDirr:
+ case X86::MMX_PUNPCKLWDrr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKLWD, m)
- case X86::MMX_PUNPCKLWDirm:
+ case X86::MMX_PUNPCKLWDrm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
DecodeUNPCKLMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
break;
CASE_UNPCK(PUNPCKLDQ, r)
- case X86::MMX_PUNPCKLDQirr:
+ case X86::MMX_PUNPCKLDQrr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKLDQ, m)
- case X86::MMX_PUNPCKLDQirm:
+ case X86::MMX_PUNPCKLDQrm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
diff --git a/llvm/lib/Target/X86/X86InstrFoldTables.cpp b/llvm/lib/Target/X86/X86InstrFoldTables.cpp
index 6d4ad08842c76..008d9684e6563 100644
--- a/llvm/lib/Target/X86/X86InstrFoldTables.cpp
+++ b/llvm/lib/Target/X86/X86InstrFoldTables.cpp
@@ -1340,28 +1340,28 @@ static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
{ X86::MINSSrr, X86::MINSSrm, 0 },
{ X86::MINSSrr_Int, X86::MINSSrm_Int, TB_NO_REVERSE },
{ X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
- { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
- { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
- { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
- { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
- { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
- { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
- { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
- { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
- { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
- { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
- { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
+ { X86::MMX_PACKSSDWrr, X86::MMX_PACKSSDWrm, 0 },
+ { X86::MMX_PACKSSWBrr, X86::MMX_PACKSSWBrm, 0 },
+ { X86::MMX_PACKUSWBrr, X86::MMX_PACKUSWBrm, 0 },
+ { X86::MMX_PADDBrr, X86::MMX_PADDBrm, 0 },
+ { X86::MMX_PADDDrr, X86::MMX_PADDDrm, 0 },
+ { X86::MMX_PADDQrr, X86::MMX_PADDQrm, 0 },
+ { X86::MMX_PADDSBrr, X86::MMX_PADDSBrm, 0 },
+ { X86::MMX_PADDSWrr, X86::MMX_PADDSWrm, 0 },
+ { X86::MMX_PADDUSBrr, X86::MMX_PADDUSBrm, 0 },
+ { X86::MMX_PADDUSWrr, X86::MMX_PADDUSWrm, 0 },
+ { X86::MMX_PADDWrr, X86::MMX_PADDWrm, 0 },
{ X86::MMX_PALIGNRrri, X86::MMX_PALIGNRrmi, 0 },
- { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
- { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
- { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
- { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
- { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
- { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
- { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
- { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
- { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
- { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
+ { X86::MMX_PANDNrr, X86::MMX_PANDNrm, 0 },
+ { X86::MMX_PANDrr, X86::MMX_PANDrm, 0 },
+ { X86::MMX_PAVGBrr, X86::MMX_PAVGBrm, 0 },
+ { X86::MMX_PAVGWrr, X86::MMX_PAVGWrm, 0 },
+ { X86::MMX_PCMPEQBrr, X86::MMX_PCMPEQBrm, 0 },
+ { X86::MMX_PCMPEQDrr, X86::MMX_PCMPEQDrm, 0 },
+ { X86::MMX_PCMPEQWrr, X86::MMX_PCMPEQWrm, 0 },
+ { X86::MMX_PCMPGTBrr, X86::MMX_PCMPGTBrm, 0 },
+ { X86::MMX_PCMPGTDrr, X86::MMX_PCMPGTDrm, 0 },
+ { X86::MMX_PCMPGTWrr, X86::MMX_PCMPGTWrm, 0 },
{ X86::MMX_PHADDDrr, X86::MMX_PHADDDrm, 0 },
{ X86::MMX_PHADDSWrr, X86::MMX_PHADDSWrm, 0 },
{ X86::MMX_PHADDWrr, X86::MMX_PHADDWrm, 0 },
@@ -1370,18 +1370,18 @@ static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
{ X86::MMX_PHSUBWrr, X86::MMX_PHSUBWrm, 0 },
{ X86::MMX_PINSRWrr, X86::MMX_PINSRWrm, TB_NO_REVERSE },
{ X86::MMX_PMADDUBSWrr, X86::MMX_PMADDUBSWrm, 0 },
- { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
- { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
- { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
- { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
- { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
+ { X86::MMX_PMADDWDrr, X86::MMX_PMADDWDrm, 0 },
+ { X86::MMX_PMAXSWrr, X86::MMX_PMAXSWrm, 0 },
+ { X86::MMX_PMAXUBrr, X86::MMX_PMAXUBrm, 0 },
+ { X86::MMX_PMINSWrr, X86::MMX_PMINSWrm, 0 },
+ { X86::MMX_PMINUBrr, X86::MMX_PMINUBrm, 0 },
{ X86::MMX_PMULHRSWrr, X86::MMX_PMULHRSWrm, 0 },
- { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
- { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
- { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
- { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
- { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
- { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
+ { X86::MMX_PMULHUWrr, X86::MMX_PMULHUWrm, 0 },
+ { X86::MMX_PMULHWrr, X86::MMX_PMULHWrm, 0 },
+ { X86::MMX_PMULLWrr, X86::MMX_PMULLWrm, 0 },
+ { X86::MMX_PMULUDQrr, X86::MMX_PMULUDQrm, 0 },
+ { X86::MMX_PORrr, X86::MMX_PORrm, 0 },
+ { X86::MMX_PSADBWrr, X86::MMX_PSADBWrm, 0 },
{ X86::MMX_PSHUFBrr, X86::MMX_PSHUFBrm, 0 },
{ X86::MMX_PSIGNBrr, X86::MMX_PSIGNBrm, 0 },
{ X86::MMX_PSIGNDrr, X86::MMX_PSIGNDrm, 0 },
@@ -1394,21 +1394,21 @@ static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
{ X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
{ X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
{ X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
- { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
- { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
- { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
- { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
- { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
- { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
- { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
- { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
- { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
- { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
- { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
- { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, TB_NO_REVERSE },
- { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, TB_NO_REVERSE },
- { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, TB_NO_REVERSE },
- { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
+ { X86::MMX_PSUBBrr, X86::MMX_PSUBBrm, 0 },
+ { X86::MMX_PSUBDrr, X86::MMX_PSUBDrm, 0 },
+ { X86::MMX_PSUBQrr, X86::MMX_PSUBQrm, 0 },
+ { X86::MMX_PSUBSBrr, X86::MMX_PSUBSBrm, 0 },
+ { X86::MMX_PSUBSWrr, X86::MMX_PSUBSWrm, 0 },
+ { X86::MMX_PSUBUSBrr, X86::MMX_PSUBUSBrm, 0 },
+ { X86::MMX_PSUBUSWrr, X86::MMX_PSUBUSWrm, 0 },
+ { X86::MMX_PSUBWrr, X86::MMX_PSUBWrm, 0 },
+ { X86::MMX_PUNPCKHBWrr, X86::MMX_PUNPCKHBWrm, 0 },
+ { X86::MMX_PUNPCKHDQrr, X86::MMX_PUNPCKHDQrm, 0 },
+ { X86::MMX_PUNPCKHWDrr, X86::MMX_PUNPCKHWDrm, 0 },
+ { X86::MMX_PUNPCKLBWrr, X86::MMX_PUNPCKLBWrm, TB_NO_REVERSE },
+ { X86::MMX_PUNPCKLDQrr, X86::MMX_PUNPCKLDQrm, TB_NO_REVERSE },
+ { X86::MMX_PUNPCKLWDrr, X86::MMX_PUNPCKLWDrm, TB_NO_REVERSE },
+ { X86::MMX_PXORrr, X86::MMX_PXORrm, 0 },
{ X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
{ X86::MOVSDrr, X86::MOVLPDrm, TB_NO_REVERSE },
{ X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index ec5d2ac3a5d6e..c379aa8d9258f 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4883,7 +4883,7 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
case X86::SETB_C64r:
return Expand2AddrUndef(MIB, get(X86::SBB64rr));
case X86::MMX_SET0:
- return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
+ return Expand2AddrUndef(MIB, get(X86::MMX_PXORrr));
case X86::V_SET0:
case X86::FsFLD0SS:
case X86::FsFLD0SD:
@@ -5156,12 +5156,12 @@ static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
bool ForLoadFold = false) {
// Set the OpNum parameter to the first source operand.
switch (Opcode) {
- case X86::MMX_PUNPCKHBWirr:
- case X86::MMX_PUNPCKHWDirr:
- case X86::MMX_PUNPCKHDQirr:
- case X86::MMX_PUNPCKLBWirr:
- case X86::MMX_PUNPCKLWDirr:
- case X86::MMX_PUNPCKLDQirr:
+ case X86::MMX_PUNPCKHBWrr:
+ case X86::MMX_PUNPCKHWDrr:
+ case X86::MMX_PUNPCKHDQrr:
+ case X86::MMX_PUNPCKLBWrr:
+ case X86::MMX_PUNPCKLWDrr:
+ case X86::MMX_PUNPCKLDQrr:
case X86::MOVHLPSrr:
case X86::PACKSSWBrr:
case X86::PACKUSWBrr:
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td
index bb3e6df3bf3e0..915161eefd962 100644
--- a/llvm/lib/Target/X86/X86InstrMMX.td
+++ b/llvm/lib/Target/X86/X86InstrMMX.td
@@ -34,14 +34,14 @@ let Constraints = "$src1 = $dst" in {
multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
X86FoldableSchedWrite sched, bit Commutable = 0,
X86MemOperand OType = i64mem> {
- def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
+ def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
(ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
Sched<[sched]> {
let isCommutable = Commutable;
}
- def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
+ def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
(ins VR64:$src1, OType:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1, (load_mmx addr:$src2)))]>,
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 2827981b7fb0a..003aa94d518dc 100644
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -800,9 +800,9 @@ def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWirr,
- MMX_PACKSSWBirr,
- MMX_PACKUSWBirr)>;
+def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWrr,
+ MMX_PACKSSWBrr,
+ MMX_PACKUSWBrr)>;
def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
let Latency = 3;
@@ -1086,9 +1086,9 @@ def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWirm,
- MMX_PACKSSWBirm,
- MMX_PACKUSWBirm)>;
+def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWrm,
+ MMX_PACKSSWBrm,
+ MMX_PACKUSWBrm)>;
def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
let Latency = 7;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 68961d6245abd..ecdcaefb38512 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -1164,9 +1164,9 @@ def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWirm,
- MMX_PACKSSWBirm,
- MMX_PACKUSWBirm)>;
+def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWrm,
+ MMX_PACKSSWBrm,
+ MMX_PACKUSWBrm)>;
def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> {
let Latency = 7;
@@ -1285,9 +1285,9 @@ def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWirr,
- MMX_PACKSSWBirr,
- MMX_PACKUSWBirr)>;
+def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWrr,
+ MMX_PACKSSWBrr,
+ MMX_PACKUSWBrr)>;
def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {
let Latency = 3;
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td
index a7b0db24df092..f9334b236dc7c 100644
--- a/llvm/lib/Target/X86/X86SchedIceLake.td
+++ b/llvm/lib/Target/X86/X86SchedIceLake.td
@@ -642,15 +642,15 @@ def: InstRW<[ICXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
"KXOR(B|D|Q|W)rr",
"KSET0(B|D|Q|W)", // Same as KXOR
"KSET1(B|D|Q|W)", // Same as KXNOR
- "MMX_PADDS(B|W)irr",
- "MMX_PADDUS(B|W)irr",
- "MMX_PAVG(B|W)irr",
- "MMX_PCMPEQ(B|D|W)irr",
- "MMX_PCMPGT(B|D|W)irr",
- "MMX_P(MAX|MIN)SWirr",
- "MMX_P(MAX|MIN)UBirr",
- "MMX_PSUBS(B|W)irr",
- "MMX_PSUBUS(B|W)irr",
+ "MMX_PADDS(B|W)rr",
+ "MMX_PADDUS(B|W)rr",
+ "MMX_PAVG(B|W)rr",
+ "MMX_PCMPEQ(B|D|W)rr",
+ "MMX_PCMPGT(B|D|W)rr",
+ "MMX_P(MAX|MIN)SWrr",
+ "MMX_P(MAX|MIN)UBrr",
+ "MMX_PSUBS(B|W)rr",
+ "MMX_PSUBUS(B|W)rr",
"VPMOVB2M(Z|Z128|Z256)rr",
"VPMOVD2M(Z|Z128|Z256)rr",
"VPMOVQ2M(Z|Z128|Z256)rr",
@@ -892,9 +892,9 @@ def ICXWriteResGroup41 : SchedWriteRes<[ICXPort5,ICXPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[ICXWriteResGroup41], (instrs MMX_PACKSSDWirr,
- MMX_PACKSSWBirr,
- MMX_PACKUSWBirr)>;
+def: InstRW<[ICXWriteResGroup41], (instrs MMX_PACKSSDWrr,
+ MMX_PACKSSWBrr,
+ MMX_PACKUSWBrr)>;
def ICXWriteResGroup42 : SchedWriteRes<[ICXPort6,ICXPort0156]> {
let Latency = 3;
@@ -1174,26 +1174,26 @@ def ICXWriteResGroup73 : SchedWriteRes<[ICXPort0,ICXPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBirm,
- MMX_PADDSWirm,
- MMX_PADDUSBirm,
- MMX_PADDUSWirm,
- MMX_PAVGBirm,
- MMX_PAVGWirm,
- MMX_PCMPEQBirm,
- MMX_PCMPEQDirm,
- MMX_PCMPEQWirm,
- MMX_PCMPGTBirm,
- MMX_PCMPGTDirm,
- MMX_PCMPGTWirm,
- MMX_PMAXSWirm,
- MMX_PMAXUBirm,
- MMX_PMINSWirm,
- MMX_PMINUBirm,
- MMX_PSUBSBirm,
- MMX_PSUBSWirm,
- MMX_PSUBUSBirm,
- MMX_PSUBUSWirm)>;
+def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBrm,
+ MMX_PADDSWrm,
+ MMX_PADDUSBrm,
+ MMX_PADDUSWrm,
+ MMX_PAVGBrm,
+ MMX_PAVGWrm,
+ MMX_PCMPEQBrm,
+ MMX_PCMPEQDrm,
+ MMX_PCMPEQWrm,
+ MMX_PCMPGTBrm,
+ MMX_PCMPGTDrm,
+ MMX_PCMPGTWrm,
+ MMX_PMAXSWrm,
+ MMX_PMAXUBrm,
+ MMX_PMINSWrm,
+ MMX_PMINUBrm,
+ MMX_PSUBSBrm,
+ MMX_PSUBSWrm,
+ MMX_PSUBUSBrm,
+ MMX_PSUBUSWrm)>;
def ICXWriteResGroup76 : SchedWriteRes<[ICXPort6,ICXPort23]> {
let Latency = 6;
@@ -1391,9 +1391,9 @@ def ICXWriteResGroup96 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[ICXWriteResGroup96], (instrs MMX_PACKSSDWirm,
- MMX_PACKSSWBirm,
- MMX_PACKUSWBirm)>;
+def: InstRW<[ICXWriteResGroup96], (instrs MMX_PACKSSDWrm,
+ MMX_PACKSSWBrm,
+ MMX_PACKUSWBrm)>;
def ICXWriteResGroup97 : SchedWriteRes<[ICXPort5,ICXPort015]> {
let Latency = 7;
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index c8d7b0f72c1c9..af5c0540deb54 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -623,7 +623,7 @@ def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr,
MMX_PABSDrr,
MMX_PABSWrr,
- MMX_PADDQirr,
+ MMX_PADDQrr,
MMX_PALIGNRrri,
MMX_PSIGNBrr,
MMX_PSIGNDrr,
@@ -870,7 +870,7 @@ def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQirm)>;
+def: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQrm)>;
def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> {
let Latency = 7;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 7d3229c3b023b..9f1df2463104f 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -624,15 +624,15 @@ def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr",
- "MMX_PADDUS(B|W)irr",
- "MMX_PAVG(B|W)irr",
- "MMX_PCMPEQ(B|D|W)irr",
- "MMX_PCMPGT(B|D|W)irr",
- "MMX_P(MAX|MIN)SWirr",
- "MMX_P(MAX|MIN)UBirr",
- "MMX_PSUBS(B|W)irr",
- "MMX_PSUBUS(B|W)irr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)rr",
+ "MMX_PADDUS(B|W)rr",
+ "MMX_PAVG(B|W)rr",
+ "MMX_PCMPEQ(B|D|W)rr",
+ "MMX_PCMPGT(B|D|W)rr",
+ "MMX_P(MAX|MIN)SWrr",
+ "MMX_P(MAX|MIN)UBrr",
+ "MMX_PSUBS(B|W)rr",
+ "MMX_PSUBUS(B|W)rr")>;
def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
let Latency = 1;
@@ -815,9 +815,9 @@ def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWirr,
- MMX_PACKSSWBirr,
- MMX_PACKUSWBirr)>;
+def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr,
+ MMX_PACKSSWBrr,
+ MMX_PACKUSWBrr)>;
def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 3;
@@ -991,26 +991,26 @@ def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBirm,
- MMX_PADDSWirm,
- MMX_PADDUSBirm,
- MMX_PADDUSWirm,
- MMX_PAVGBirm,
- MMX_PAVGWirm,
- MMX_PCMPEQBirm,
- MMX_PCMPEQDirm,
- MMX_PCMPEQWirm,
- MMX_PCMPGTBirm,
- MMX_PCMPGTDirm,
- MMX_PCMPGTWirm,
- MMX_PMAXSWirm,
- MMX_PMAXUBirm,
- MMX_PMINSWirm,
- MMX_PMINUBirm,
- MMX_PSUBSBirm,
- MMX_PSUBSWirm,
- MMX_PSUBUSBirm,
- MMX_PSUBUSWirm)>;
+def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm,
+ MMX_PADDSWrm,
+ MMX_PADDUSBrm,
+ MMX_PADDUSWrm,
+ MMX_PAVGBrm,
+ MMX_PAVGWrm,
+ MMX_PCMPEQBrm,
+ MMX_PCMPEQDrm,
+ MMX_PCMPEQWrm,
+ MMX_PCMPGTBrm,
+ MMX_PCMPGTDrm,
+ MMX_PCMPGTWrm,
+ MMX_PMAXSWrm,
+ MMX_PMAXUBrm,
+ MMX_PMINSWrm,
+ MMX_PMINUBrm,
+ MMX_PSUBSBrm,
+ MMX_PSUBSWrm,
+ MMX_PSUBUSBrm,
+ MMX_PSUBUSWrm)>;
def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> {
let Latency = 6;
@@ -1144,9 +1144,9 @@ def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWirm,
- MMX_PACKSSWBirm,
- MMX_PACKUSWBirm)>;
+def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWrm,
+ MMX_PACKSSWBrm,
+ MMX_PACKUSWBrm)>;
def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
let Latency = 7;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index db32d032aa07f..ffccb3bba1705 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -634,15 +634,15 @@ def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
"KXOR(B|D|Q|W)rr",
"KSET0(B|D|Q|W)", // Same as KXOR
"KSET1(B|D|Q|W)", // Same as KXNOR
- "MMX_PADDS(B|W)irr",
- "MMX_PADDUS(B|W)irr",
- "MMX_PAVG(B|W)irr",
- "MMX_PCMPEQ(B|D|W)irr",
- "MMX_PCMPGT(B|D|W)irr",
- "MMX_P(MAX|MIN)SWirr",
- "MMX_P(MAX|MIN)UBirr",
- "MMX_PSUBS(B|W)irr",
- "MMX_PSUBUS(B|W)irr",
+ "MMX_PADDS(B|W)rr",
+ "MMX_PADDUS(B|W)rr",
+ "MMX_PAVG(B|W)rr",
+ "MMX_PCMPEQ(B|D|W)rr",
+ "MMX_PCMPGT(B|D|W)rr",
+ "MMX_P(MAX|MIN)SWrr",
+ "MMX_P(MAX|MIN)UBrr",
+ "MMX_PSUBS(B|W)rr",
+ "MMX_PSUBUS(B|W)rr",
"VPMOVB2M(Z|Z128|Z256)rr",
"VPMOVD2M(Z|Z128|Z256)rr",
"VPMOVQ2M(Z|Z128|Z256)rr",
@@ -884,9 +884,9 @@ def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWirr,
- MMX_PACKSSWBirr,
- MMX_PACKUSWBirr)>;
+def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWrr,
+ MMX_PACKSSWBrr,
+ MMX_PACKUSWBrr)>;
def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
let Latency = 3;
@@ -1166,26 +1166,26 @@ def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBirm,
- MMX_PADDSWirm,
- MMX_PADDUSBirm,
- MMX_PADDUSWirm,
- MMX_PAVGBirm,
- MMX_PAVGWirm,
- MMX_PCMPEQBirm,
- MMX_PCMPEQDirm,
- MMX_PCMPEQWirm,
- MMX_PCMPGTBirm,
- MMX_PCMPGTDirm,
- MMX_PCMPGTWirm,
- MMX_PMAXSWirm,
- MMX_PMAXUBirm,
- MMX_PMINSWirm,
- MMX_PMINUBirm,
- MMX_PSUBSBirm,
- MMX_PSUBSWirm,
- MMX_PSUBUSBirm,
- MMX_PSUBUSWirm)>;
+def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBrm,
+ MMX_PADDSWrm,
+ MMX_PADDUSBrm,
+ MMX_PADDUSWrm,
+ MMX_PAVGBrm,
+ MMX_PAVGWrm,
+ MMX_PCMPEQBrm,
+ MMX_PCMPEQDrm,
+ MMX_PCMPEQWrm,
+ MMX_PCMPGTBrm,
+ MMX_PCMPGTDrm,
+ MMX_PCMPGTWrm,
+ MMX_PMAXSWrm,
+ MMX_PMAXUBrm,
+ MMX_PMINSWrm,
+ MMX_PMINUBrm,
+ MMX_PSUBSBrm,
+ MMX_PSUBSWrm,
+ MMX_PSUBUSBrm,
+ MMX_PSUBUSWrm)>;
def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
let Latency = 6;
@@ -1383,9 +1383,9 @@ def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWirm,
- MMX_PACKSSWBirm,
- MMX_PACKUSWBirm)>;
+def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWrm,
+ MMX_PACKSSWBrm,
+ MMX_PACKUSWBrm)>;
def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let Latency = 7;
diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td
index 6fd98280f560c..8b34b1fd85d26 100644
--- a/llvm/lib/Target/X86/X86ScheduleAtom.td
+++ b/llvm/lib/Target/X86/X86ScheduleAtom.td
@@ -570,7 +570,7 @@ def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r,
SCASB, SCASL, SCASQ, SCASW)>;
def : InstRW<[AtomWrite01_2], (instregex "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)",
"(ST|ISTT)_F(P)?(16|32|64)?(m|rr)",
- "MMX_P(ADD|SUB)Qirr",
+ "MMX_P(ADD|SUB)Qrr",
"MOV(S|Z)X16rr8",
"MOV(UPS|UPD|DQU)mr",
"MASKMOVDQU(64)?",
@@ -589,7 +589,7 @@ def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",
"XCHG(8|16|32|64)rm",
"PH(ADD|SUB)Drr",
"MOV(S|Z)X16rm8",
- "MMX_P(ADD|SUB)Qirm",
+ "MMX_P(ADD|SUB)Qrm",
"MOV(UPS|UPD|DQU)rm",
"P(ADD|SUB)Qrm")>;
diff --git a/llvm/lib/Target/X86/X86ScheduleBdVer2.td b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
index 4c16b5b52b1d0..7ea26abaca9e2 100644
--- a/llvm/lib/Target/X86/X86ScheduleBdVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
@@ -1365,7 +1365,7 @@ def PdWriteVZeroIdiomLogic : SchedWriteVariant<[
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [PdWriteZeroLatency]>,
SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogic]>
]>;
-def : InstRW<[PdWriteVZeroIdiomLogic], (instrs MMX_PXORirr, MMX_PANDNirr)>;
+def : InstRW<[PdWriteVZeroIdiomLogic], (instrs MMX_PXORrr, MMX_PANDNrr)>;
def PdWriteVZeroIdiomLogicX : SchedWriteVariant<[
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [PdWriteZeroLatency]>,
@@ -1378,11 +1378,11 @@ def PdWriteVZeroIdiomALU : SchedWriteVariant<[
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [PdWriteZeroLatency]>,
SchedVar<MCSchedPredicate<TruePred>, [WriteVecALU]>
]>;
-def : InstRW<[PdWriteVZeroIdiomALU], (instrs MMX_PSUBBirr, MMX_PSUBDirr,
- MMX_PSUBQirr, MMX_PSUBWirr,
- MMX_PCMPGTBirr,
- MMX_PCMPGTDirr,
- MMX_PCMPGTWirr)>;
+def : InstRW<[PdWriteVZeroIdiomALU], (instrs MMX_PSUBBrr, MMX_PSUBDrr,
+ MMX_PSUBQrr, MMX_PSUBWrr,
+ MMX_PCMPGTBrr,
+ MMX_PCMPGTDrr,
+ MMX_PCMPGTWrr)>;
def PdWriteVZeroIdiomALUX : SchedWriteVariant<[
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [PdWriteZeroLatency]>,
@@ -1408,10 +1408,10 @@ def : IsZeroIdiomFunction<[
// MMX Zero-idioms.
DepBreakingClass<[
- MMX_PXORirr, MMX_PANDNirr, MMX_PSUBBirr,
- MMX_PSUBDirr, MMX_PSUBQirr, MMX_PSUBWirr,
- MMX_PSUBSBirr, MMX_PSUBSWirr, MMX_PSUBUSBirr, MMX_PSUBUSWirr,
- MMX_PCMPGTBirr, MMX_PCMPGTDirr, MMX_PCMPGTWirr
+ MMX_PXORrr, MMX_PANDNrr, MMX_PSUBBrr,
+ MMX_PSUBDrr, MMX_PSUBQrr, MMX_PSUBWrr,
+ MMX_PSUBSBrr, MMX_PSUBSWrr, MMX_PSUBUSBrr, MMX_PSUBUSWrr,
+ MMX_PCMPGTBrr, MMX_PCMPGTDrr, MMX_PCMPGTWrr
], ZeroIdiomPredicate>,
// SSE Zero-idioms.
@@ -1449,7 +1449,7 @@ def : IsDepBreakingFunction<[
// MMX
DepBreakingClass<[
- MMX_PCMPEQBirr, MMX_PCMPEQDirr, MMX_PCMPEQWirr
+ MMX_PCMPEQBrr, MMX_PCMPEQDrr, MMX_PCMPEQWrr
], ZeroIdiomPredicate>,
// SSE
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
index 68ebaa244acf1..a070da34cab50 100644
--- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
@@ -888,7 +888,7 @@ def JWriteVZeroIdiomLogic : SchedWriteVariant<[
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecLogic]>
]>;
-def : InstRW<[JWriteVZeroIdiomLogic], (instrs MMX_PXORirr, MMX_PANDNirr)>;
+def : InstRW<[JWriteVZeroIdiomLogic], (instrs MMX_PXORrr, MMX_PANDNrr)>;
def JWriteVZeroIdiomLogicX : SchedWriteVariant<[
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
@@ -901,12 +901,12 @@ def JWriteVZeroIdiomALU : SchedWriteVariant<[
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecALU]>
]>;
-def : InstRW<[JWriteVZeroIdiomALU], (instrs MMX_PSUBBirr, MMX_PSUBDirr,
- MMX_PSUBQirr, MMX_PSUBWirr,
- MMX_PSUBSBirr, MMX_PSUBSWirr,
- MMX_PSUBUSBirr, MMX_PSUBUSWirr,
- MMX_PCMPGTBirr, MMX_PCMPGTDirr,
- MMX_PCMPGTWirr)>;
+def : InstRW<[JWriteVZeroIdiomALU], (instrs MMX_PSUBBrr, MMX_PSUBDrr,
+ MMX_PSUBQrr, MMX_PSUBWrr,
+ MMX_PSUBSBrr, MMX_PSUBSWrr,
+ MMX_PSUBUSBrr, MMX_PSUBUSWrr,
+ MMX_PCMPGTBrr, MMX_PCMPGTDrr,
+ MMX_PCMPGTWrr)>;
def JWriteVZeroIdiomALUX : SchedWriteVariant<[
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
@@ -974,10 +974,10 @@ def : IsZeroIdiomFunction<[
// MMX Zero-idioms.
DepBreakingClass<[
- MMX_PXORirr, MMX_PANDNirr, MMX_PSUBBirr,
- MMX_PSUBDirr, MMX_PSUBQirr, MMX_PSUBWirr,
- MMX_PSUBSBirr, MMX_PSUBSWirr, MMX_PSUBUSBirr, MMX_PSUBUSWirr,
- MMX_PCMPGTBirr, MMX_PCMPGTDirr, MMX_PCMPGTWirr
+ MMX_PXORrr, MMX_PANDNrr, MMX_PSUBBrr,
+ MMX_PSUBDrr, MMX_PSUBQrr, MMX_PSUBWrr,
+ MMX_PSUBSBrr, MMX_PSUBSWrr, MMX_PSUBUSBrr, MMX_PSUBUSWrr,
+ MMX_PCMPGTBrr, MMX_PCMPGTDrr, MMX_PCMPGTWrr
], ZeroIdiomPredicate>,
// SSE Zero-idioms.
@@ -1017,7 +1017,7 @@ def : IsDepBreakingFunction<[
// MMX
DepBreakingClass<[
- MMX_PCMPEQBirr, MMX_PCMPEQDirr, MMX_PCMPEQWirr
+ MMX_PCMPEQBrr, MMX_PCMPEQDrr, MMX_PCMPEQWrr
], ZeroIdiomPredicate>,
// SSE
diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td
index 5af9835f75a74..36e5b55a41944 100644
--- a/llvm/lib/Target/X86/X86ScheduleSLM.td
+++ b/llvm/lib/Target/X86/X86ScheduleSLM.td
@@ -467,8 +467,8 @@ def SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> {
let NumMicroOps = 2;
let ResourceCycles = [8];
}
-def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQirr, PADDQrr,
- MMX_PSUBQirr, PSUBQrr,
+def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr,
+ MMX_PSUBQrr, PSUBQrr,
PCMPEQQrr)>;
def SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> {
@@ -476,8 +476,8 @@ def SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> {
let NumMicroOps = 3;
let ResourceCycles = [1,8];
}
-def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQirm, PADDQrm,
- MMX_PSUBQirm, PSUBQrm,
+def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm,
+ MMX_PSUBQrm, PSUBQrm,
PCMPEQQrm)>;
} // SchedModel
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index 8e30e5e10ca80..d75f164f2e511 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -1000,12 +1000,12 @@ def ZnWriteFPU12Ym : SchedWriteRes<[ZnAGU, ZnFPU12]> {
let NumMicroOps = 2;
}
-def : InstRW<[ZnWriteFPU12], (instrs MMX_PACKSSDWirr,
- MMX_PACKSSWBirr,
- MMX_PACKUSWBirr)>;
-def : InstRW<[ZnWriteFPU12m], (instrs MMX_PACKSSDWirm,
- MMX_PACKSSWBirm,
- MMX_PACKUSWBirm)>;
+def : InstRW<[ZnWriteFPU12], (instrs MMX_PACKSSDWrr,
+ MMX_PACKSSWBrr,
+ MMX_PACKUSWBrr)>;
+def : InstRW<[ZnWriteFPU12m], (instrs MMX_PACKSSDWrm,
+ MMX_PACKSSWBrm,
+ MMX_PACKUSWBrm)>;
def ZnWriteFPU013 : SchedWriteRes<[ZnFPU013]> ;
def ZnWriteFPU013Y : SchedWriteRes<[ZnFPU013]> {
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver2.td b/llvm/lib/Target/X86/X86ScheduleZnver2.td
index a83c89e2f28a0..e597d4001bc99 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver2.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver2.td
@@ -1012,12 +1012,12 @@ def Zn2WriteFPU12Ym : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
let NumMicroOps = 2;
}
-def : InstRW<[Zn2WriteFPU12], (instrs MMX_PACKSSDWirr,
- MMX_PACKSSWBirr,
- MMX_PACKUSWBirr)>;
-def : InstRW<[Zn2WriteFPU12m], (instrs MMX_PACKSSDWirm,
- MMX_PACKSSWBirm,
- MMX_PACKUSWBirm)>;
+def : InstRW<[Zn2WriteFPU12], (instrs MMX_PACKSSDWrr,
+ MMX_PACKSSWBrr,
+ MMX_PACKUSWBrr)>;
+def : InstRW<[Zn2WriteFPU12m], (instrs MMX_PACKSSDWrm,
+ MMX_PACKSSWBrm,
+ MMX_PACKUSWBrm)>;
def Zn2WriteFPU013 : SchedWriteRes<[Zn2FPU013]> ;
def Zn2WriteFPU013Y : SchedWriteRes<[Zn2FPU013]> ;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver3.td b/llvm/lib/Target/X86/X86ScheduleZnver3.td
index be07c069aae10..bbc5f36c693af 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver3.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver3.td
@@ -1075,9 +1075,9 @@ def Zn3WriteVecALUXMMX : SchedWriteRes<[Zn3FPVAdd01]> {
}
def : InstRW<[Zn3WriteVecALUXMMX], (instrs MMX_PABSBrr, MMX_PABSDrr, MMX_PABSWrr,
MMX_PSIGNBrr, MMX_PSIGNDrr, MMX_PSIGNWrr,
- MMX_PADDSBirr, MMX_PADDSWirr, MMX_PADDUSBirr, MMX_PADDUSWirr,
- MMX_PAVGBirr, MMX_PAVGWirr,
- MMX_PSUBSBirr, MMX_PSUBSWirr, MMX_PSUBUSBirr, MMX_PSUBUSWirr)>;
+ MMX_PADDSBrr, MMX_PADDSWrr, MMX_PADDUSBrr, MMX_PADDUSWrr,
+ MMX_PAVGBrr, MMX_PAVGWrr,
+ MMX_PSUBSBrr, MMX_PSUBSWrr, MMX_PSUBUSBrr, MMX_PSUBUSWrr)>;
defm : Zn3WriteResYMMPair<WriteVecALUY, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no logicals (YMM).
@@ -1621,7 +1621,7 @@ def : IsDepBreakingFunction<[
// MMX
DepBreakingClass<[
- MMX_PCMPEQBirr, MMX_PCMPEQWirr, MMX_PCMPEQDirr
+ MMX_PCMPEQBrr, MMX_PCMPEQWrr, MMX_PCMPEQDrr
], ZeroIdiomPredicate>,
// SSE
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