[llvm] 67aeae0 - [llvm] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sat Dec 11 22:34:19 PST 2021
Author: Kazu Hirata
Date: 2021-12-11T22:34:07-08:00
New Revision: 67aeae0138ff1eac07165f247e39a3bdaa5b17a4
URL: https://github.com/llvm/llvm-project/commit/67aeae0138ff1eac07165f247e39a3bdaa5b17a4
DIFF: https://github.com/llvm/llvm-project/commit/67aeae0138ff1eac07165f247e39a3bdaa5b17a4.diff
LOG: [llvm] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/CodeGen/VLIWMachineScheduler.cpp
llvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp
llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
llvm/lib/Target/AMDGPU/R600Packetizer.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/VLIWMachineScheduler.cpp b/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
index 7e8cd2769a4c..cbc5d9ec169b 100644
--- a/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
+++ b/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
@@ -219,16 +219,20 @@ void VLIWMachineScheduler::schedule() {
// Initialize the strategy before modifying the DAG.
SchedImpl->initialize(this);
- LLVM_DEBUG(unsigned maxH = 0;
- for (unsigned su = 0, e = SUnits.size(); su != e;
- ++su) if (SUnits[su].getHeight() > maxH) maxH =
- SUnits[su].getHeight();
- dbgs() << "Max Height " << maxH << "\n";);
- LLVM_DEBUG(unsigned maxD = 0;
- for (unsigned su = 0, e = SUnits.size(); su != e;
- ++su) if (SUnits[su].getDepth() > maxD) maxD =
- SUnits[su].getDepth();
- dbgs() << "Max Depth " << maxD << "\n";);
+ LLVM_DEBUG({
+ unsigned maxH = 0;
+ for (const SUnit &SU : SUnits)
+ if (SU.getHeight() > maxH)
+ maxH = SU.getHeight();
+ dbgs() << "Max Height " << maxH << "\n";
+ });
+ LLVM_DEBUG({
+ unsigned maxD = 0;
+ for (const SUnit &SU : SUnits)
+ if (SU.getDepth() > maxD)
+ maxD = SU.getDepth();
+ dbgs() << "Max Depth " << maxD << "\n";
+ });
LLVM_DEBUG(dump());
if (ViewMISchedDAGs)
viewGraph();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp
index ee944d22f98e..2a2338ac7016 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp
@@ -403,8 +403,8 @@ class CollectReachableCallees {
void collectAddressTakenFunctions() {
auto *ECNode = CG.getExternalCallingNode();
- for (auto GI = ECNode->begin(), GE = ECNode->end(); GI != GE; ++GI) {
- auto *CGN = GI->second;
+ for (const auto &GI : *ECNode) {
+ auto *CGN = GI.second;
auto *F = CGN->getFunction();
if (!F || F->isDeclaration() || llvm::AMDGPU::isKernelCC(F))
continue;
@@ -441,9 +441,9 @@ class CollectReachableCallees {
if (!CGN->getFunction() || CGN->getFunction()->isDeclaration())
continue;
- for (auto GI = CGN->begin(), GE = CGN->end(); GI != GE; ++GI) {
- auto *RCB = cast<CallBase>(GI->first.getValue());
- auto *RCGN = GI->second;
+ for (const auto &GI : *CGN) {
+ auto *RCB = cast<CallBase>(GI.first.getValue());
+ auto *RCGN = GI.second;
if (auto *DCallee = RCGN->getFunction()) {
ReachableCallees.insert(DCallee);
diff --git a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
index 712f6dece911..1736c078eb83 100644
--- a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
@@ -173,10 +173,8 @@ class AMDGPUCFGStructurizer : public MachineFunctionPass {
}
static void PrintLoopinfo(const MachineLoopInfo &LoopInfo) {
- for (MachineLoop::iterator iter = LoopInfo.begin(),
- iterEnd = LoopInfo.end(); iter != iterEnd; ++iter) {
- (*iter)->print(dbgs());
- }
+ for (const MachineLoop *L : LoopInfo)
+ L->print(dbgs());
}
// UTILITY FUNCTIONS
@@ -691,9 +689,7 @@ bool AMDGPUCFGStructurizer::prepare() {
SmallVector<MachineBasicBlock *, DEFAULT_VEC_SLOTS> RetBlks;
// Add an ExitBlk to loop that don't have one
- for (MachineLoopInfo::iterator It = MLI->begin(),
- E = MLI->end(); It != E; ++It) {
- MachineLoop *LoopRep = (*It);
+ for (MachineLoop *LoopRep : *MLI) {
MBBVector ExitingMBBs;
LoopRep->getExitingBlocks(ExitingMBBs);
@@ -827,14 +823,13 @@ bool AMDGPUCFGStructurizer::run() {
wrapup(*GraphTraits<MachineFunction *>::nodes_begin(FuncRep));
// Detach retired Block, release memory.
- for (MBBInfoMap::iterator It = BlockInfoMap.begin(), E = BlockInfoMap.end();
- It != E; ++It) {
- if ((*It).second && (*It).second->IsRetired) {
- assert(((*It).first)->getNumber() != -1);
- LLVM_DEBUG(dbgs() << "Erase BB" << ((*It).first)->getNumber() << "\n";);
- (*It).first->eraseFromParent(); //Remove from the parent Function.
+ for (auto &It : BlockInfoMap) {
+ if (It.second && It.second->IsRetired) {
+ assert((It.first)->getNumber() != -1);
+ LLVM_DEBUG(dbgs() << "Erase BB" << (It.first)->getNumber() << "\n";);
+ It.first->eraseFromParent(); // Remove from the parent Function.
}
- delete (*It).second;
+ delete It.second;
}
BlockInfoMap.clear();
LLInfoMap.clear();
diff --git a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
index 29c37c706138..8a48a67b829c 100644
--- a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
@@ -440,9 +440,8 @@ class R600ControlFlowFinalizer : public MachineFunctionPass {
CounterPropagateAddr(*Clause.first, CfCount);
MachineBasicBlock *BB = Clause.first->getParent();
BuildMI(BB, DL, TII->get(R600::FETCH_CLAUSE)).addImm(CfCount);
- for (unsigned i = 0, e = Clause.second.size(); i < e; ++i) {
- BB->splice(InsertPos, BB, Clause.second[i]);
- }
+ for (MachineInstr *MI : Clause.second)
+ BB->splice(InsertPos, BB, MI);
CfCount += 2 * Clause.second.size();
}
@@ -452,9 +451,8 @@ class R600ControlFlowFinalizer : public MachineFunctionPass {
CounterPropagateAddr(*Clause.first, CfCount);
MachineBasicBlock *BB = Clause.first->getParent();
BuildMI(BB, DL, TII->get(R600::ALU_CLAUSE)).addImm(CfCount);
- for (unsigned i = 0, e = Clause.second.size(); i < e; ++i) {
- BB->splice(InsertPos, BB, Clause.second[i]);
- }
+ for (MachineInstr *MI : Clause.second)
+ BB->splice(InsertPos, BB, MI);
CfCount += Clause.second.size();
}
@@ -635,10 +633,10 @@ class R600ControlFlowFinalizer : public MachineFunctionPass {
CfCount++;
}
MI->eraseFromParent();
- for (unsigned i = 0, e = FetchClauses.size(); i < e; i++)
- EmitFetchClause(I, DL, FetchClauses[i], CfCount);
- for (unsigned i = 0, e = AluClauses.size(); i < e; i++)
- EmitALUClause(I, DL, AluClauses[i], CfCount);
+ for (ClauseFile &CF : FetchClauses)
+ EmitFetchClause(I, DL, CF, CfCount);
+ for (ClauseFile &CF : AluClauses)
+ EmitALUClause(I, DL, CF, CfCount);
break;
}
default:
@@ -649,8 +647,7 @@ class R600ControlFlowFinalizer : public MachineFunctionPass {
break;
}
}
- for (unsigned i = 0, e = ToPopAfter.size(); i < e; ++i) {
- MachineInstr *Alu = ToPopAfter[i];
+ for (MachineInstr *Alu : ToPopAfter) {
BuildMI(MBB, Alu, MBB.findDebugLoc((MachineBasicBlock::iterator)Alu),
TII->get(R600::CF_ALU_POP_AFTER))
.addImm(Alu->getOperand(0).getImm())
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index a7ebf72315cb..aec8b1ae4837 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -268,17 +268,15 @@ R600InstrInfo::getSrcs(MachineInstr &MI) const {
{R600::OpName::src1_W, R600::OpName::src1_sel_W},
};
- for (unsigned j = 0; j < 8; j++) {
- MachineOperand &MO =
- MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0]));
+ for (const auto &Op : OpTable) {
+ MachineOperand &MO = MI.getOperand(getOperandIdx(MI.getOpcode(), Op[0]));
Register Reg = MO.getReg();
if (Reg == R600::ALU_CONST) {
MachineOperand &Sel =
- MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
+ MI.getOperand(getOperandIdx(MI.getOpcode(), Op[1]));
Result.push_back(std::make_pair(&MO, Sel.getImm()));
continue;
}
-
}
return Result;
}
@@ -289,15 +287,14 @@ R600InstrInfo::getSrcs(MachineInstr &MI) const {
{R600::OpName::src2, R600::OpName::src2_sel},
};
- for (unsigned j = 0; j < 3; j++) {
- int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]);
+ for (const auto &Op : OpTable) {
+ int SrcIdx = getOperandIdx(MI.getOpcode(), Op[0]);
if (SrcIdx < 0)
break;
MachineOperand &MO = MI.getOperand(SrcIdx);
Register Reg = MO.getReg();
if (Reg == R600::ALU_CONST) {
- MachineOperand &Sel =
- MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
+ MachineOperand &Sel = MI.getOperand(getOperandIdx(MI.getOpcode(), Op[1]));
Result.push_back(std::make_pair(&MO, Sel.getImm()));
continue;
}
@@ -521,12 +518,11 @@ R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
ValidSwizzle.clear();
unsigned ConstCount;
BankSwizzle TransBS = ALU_VEC_012_SCL_210;
- for (unsigned i = 0, e = IG.size(); i < e; ++i) {
- IGSrcs.push_back(ExtractSrcs(*IG[i], PV, ConstCount));
- unsigned Op = getOperandIdx(IG[i]->getOpcode(),
- R600::OpName::bank_swizzle);
- ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
- IG[i]->getOperand(Op).getImm());
+ for (MachineInstr *MI : IG) {
+ IGSrcs.push_back(ExtractSrcs(*MI, PV, ConstCount));
+ unsigned Op = getOperandIdx(MI->getOpcode(), R600::OpName::bank_swizzle);
+ ValidSwizzle.push_back(
+ (R600InstrInfo::BankSwizzle)MI->getOperand(Op).getImm());
}
std::vector<std::pair<int, unsigned>> TransOps;
if (!isLastAluTrans)
@@ -542,8 +538,7 @@ R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
ALU_VEC_120_SCL_212,
ALU_VEC_102_SCL_221
};
- for (unsigned i = 0; i < 4; i++) {
- TransBS = TransSwz[i];
+ for (R600InstrInfo::BankSwizzle TransBS : TransSwz) {
if (!isConstCompatible(TransBS, TransOps, ConstCount))
continue;
bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
@@ -562,9 +557,9 @@ R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
const {
assert (Consts.size() <= 12 && "Too many operands in instructions group");
unsigned Pair1 = 0, Pair2 = 0;
- for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
- unsigned ReadConstHalf = Consts[i] & 2;
- unsigned ReadConstIndex = Consts[i] & (~3);
+ for (unsigned Const : Consts) {
+ unsigned ReadConstHalf = Const & 2;
+ unsigned ReadConstIndex = Const & (~3);
unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
if (!Pair1) {
Pair1 = ReadHalfConst;
@@ -587,12 +582,11 @@ R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
const {
std::vector<unsigned> Consts;
SmallSet<int64_t, 4> Literals;
- for (unsigned i = 0, n = MIs.size(); i < n; i++) {
- MachineInstr &MI = *MIs[i];
- if (!isALUInstr(MI.getOpcode()))
+ for (MachineInstr *MI : MIs) {
+ if (!isALUInstr(MI->getOpcode()))
continue;
- for (const auto &Src : getSrcs(MI)) {
+ for (const auto &Src : getSrcs(*MI)) {
if (Src.first->getReg() == R600::ALU_LITERAL_X)
Literals.insert(Src.second);
if (Literals.size() > 4)
@@ -1330,11 +1324,11 @@ MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
MIB->getOperand(getOperandIdx(Opcode, R600::OpName::pred_sel))
.setReg(MO.getReg());
- for (unsigned i = 0; i < 14; i++) {
+ for (unsigned Operand : Operands) {
MachineOperand &MO = MI->getOperand(
- getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
+ getOperandIdx(MI->getOpcode(), getSlotedOps(Operand, Slot)));
assert (MO.isImm());
- setImmOperand(*MIB, Operands[i], MO.getImm());
+ setImmOperand(*MIB, Operand, MO.getImm());
}
MIB->getOperand(20).setImm(0);
return MIB;
diff --git a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp
index beb0aad86e89..fbe2a1cd9fba 100644
--- a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp
+++ b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp
@@ -127,8 +127,8 @@ class R600PacketizerList : public VLIWPacketizerList {
R600::OpName::src1,
R600::OpName::src2
};
- for (unsigned i = 0; i < 3; i++) {
- int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]);
+ for (unsigned Op : Ops) {
+ int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Op);
if (OperandIdx < 0)
continue;
Register Src = MI.getOperand(OperandIdx).getReg();
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