[PATCH] D115396: [ASan] Replace IR based callbacks with shared assembly code callbacks.
Matt Morehouse via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 10 07:32:52 PST 2021
morehouse accepted this revision.
morehouse added inline comments.
This revision is now accepted and ready to land.
================
Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1351-1352
std::string Name = AccessInfo.IsWrite ? "store" : "load";
- MCSymbol *ReportError = OutContext.getOrCreateSymbol(
- "__asan_report_" + Name + utostr(1ULL << AccessInfo.AccessSizeIndex));
- OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
- .addReg(X86::RDI)
- .addReg(X86::NoRegister + Reg),
- STI);
- OutStreamer->emitInstruction(
- MCInstBuilder(X86::JMP_4)
- .addExpr(MCSymbolRefExpr::create(ReportError, MCSymbolRefExpr::VK_PLT,
- OutContext)),
- STI);
-}
+ std::string Op = OrShadowOffset ? "or" : "add";
+ std::string SymName = "__asan_check_" + Name + "_" + Op + "_" +
+ utostr(1ULL << AccessInfo.AccessSizeIndex) + "_" +
----------------
================
Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1351
std::string Name = AccessInfo.IsWrite ? "store" : "load";
- MCSymbol *ReportError = OutContext.getOrCreateSymbol(
- "__asan_report_" + Name + utostr(1ULL << AccessInfo.AccessSizeIndex));
- OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
- .addReg(X86::RDI)
- .addReg(X86::NoRegister + Reg),
- STI);
- OutStreamer->emitInstruction(
- MCInstBuilder(X86::JMP_4)
- .addExpr(MCSymbolRefExpr::create(ReportError, MCSymbolRefExpr::VK_PLT,
- OutContext)),
- STI);
-}
+ std::string Op = OrShadowOffset ? "or" : "add";
+ std::string SymName = "__asan_check_" + Name + "_" + Op + "_" +
----------------
kstoimenov wrote:
> morehouse wrote:
> > We didn't implement OR callbacks, did we? Probably we should not emit calls to them.
> Added llvm_unreachable.
Let's move this CHECK to right after the call to `getAddressSanitizerParams`. And let's hard code `Op` as "add".
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D115396/new/
https://reviews.llvm.org/D115396
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