[PATCH] D115457: [AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0)

[Momchil Velikov via Phabricator via llvm-commits]

chill added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11229
     if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) {
+      const bool Accumulates = any_of(Op.getNode()->uses(), [](SDNode *N) {
+        return N->getOpcode() == ISD::ADD;
----------------
dmgreen wrote:
> This add exemption makes it a bit awkward. Do we need to convert this early, or could we just add tablegen patterns and let it pick the "best" one for the given code, like it is fairly descent at.
> 
> Something like this, for each type, might be enough:
> ```
> def : Pat<(v16i8 (AArch64vashr (v16i8 V128:$Rn), (i32 7))),
>           (CMLTv16i8rz V128:$Rn)>;
> ```
Why is ADD an exception?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D115457/new/

https://reviews.llvm.org/D115457