[PATCH] D115469: [RISCV] Share tablegen classes for F, D, and Zfh. Other simplifications. NFC

[Shao-Ce SUN via Phabricator via llvm-commits]

achieveartificialintelligence added a comment.

LGTM. And this patch will improve  D93298 <https://reviews.llvm.org/D93298> a lot. Thanks!



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:61-72
+def FADD_D : FPALU_rr_frm<0b0000001, "fadd.d", FPR64>,
              Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
-def        : FPALUDDynFrmAlias<FADD_D, "fadd.d">;
-def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">,
+def        : FPALUDynFrmAlias<FADD_D, "fadd.d", FPR64>;
+def FSUB_D : FPALU_rr_frm<0b0000101, "fsub.d", FPR64>,
              Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
-def        : FPALUDDynFrmAlias<FSUB_D, "fsub.d">;
-def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">,
+def        : FPALUDynFrmAlias<FSUB_D, "fsub.d", FPR64>;
+def FMUL_D : FPALU_rr_frm<0b0001001, "fmul.d", FPR64>,
----------------
How about put Alias together?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D115469/new/

https://reviews.llvm.org/D115469