[PATCH] D113439: [RISCV] Add IR intrinsics for reading/write vxrm.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

I think at the IR level, we need the intrinsic variants that have a rounding mode argument if we want to allow the compiler to ever generate the relevant instructions for autovectorization etc.  The autovectorizer can't use vgetvrm/vsetvrm correctly and efficiently; it can't tell, for example, where the backend will insert runtime calls.

I think it makes sense to expose there variants to users directly, rather than exposing raw vgetvrm/vsetvrm.  I think the risk of confusion is minimal; if the user looks at the riscv_vector.h documentation and sees that the shift intrinsic has a "rounding mode" argument, it should be clear how to use it.  The user shouldn't need to care that the bits aren't actually part of the instruction encoding.

That said, if we really want to expose vgetvrm/vsetvrm and implicit rounding modes as C intrinsics, we can do it, I guess.  The compiler can save/restore the state if it needs to.  It makes the implementation more complicated, and the code less efficient at runtime, though.


Repository:
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  https://reviews.llvm.org/D113439/new/

https://reviews.llvm.org/D113439