[PATCH] D115469: [RISCV] Share tablegen classes for F, D, and Zfh. Other simplifications.

[Craig Topper via Phabricator via llvm-commits]

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By adding the register class and funct as template parameters we
can share the classes with all 3 extensions.

I've used "let SchedRW =" to avoid repeating scheduler classes on
multiple lines by inheriting from the Sched class.

A subsequent patch will add mayRaiseFPException and FRM dependencies.
Reducing the number of classes means less repeating for those changes.

This of course conflicts with the Zfinx patch D93298 <https://reviews.llvm.org/D93298>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115469

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

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