[PATCH] D113439: [RISCV] Add IR intrinsics for reading/write vxrm.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

If you want an example of something broken because we didn't do it correctly, look at the ARM intrinsics involving the saturation bit.  For an example of something that works... maybe the x86 "DF" flag?

Probably best to do the lowering after isel: we don't have any infrastructure for hoisting/coalescing the instructions that modify the register (unless you want to try to make the register allocator handle it).

Maybe look at X86VZeroUpper.cpp for inspiration; not exactly the same thing, but a similar algorithm should work.

How you deal with calls depends on the calling convention you want to use.  There are basically three possibilities:

1. We require that the register is zero (or some other fixed value) on entry to/return from a call.
2. The register is volatile across calls.
3. The register is preserved by calls.

It looks like the current ABI documentation says it has "thread storage duration", but that's not really a great idea; we don't want to expose this in the first place.  Hopefully this isn't set in stone?  If necessary, we could use some hack like preserving the incoming value, but assuming outgoing calls clobber it, I guess.

If you're using a state machine like X86VZeroUpper, it should be easy to handle in any case.


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