[PATCH] D111221: [AArch64][SVE] Improve code generation for VLS i1 masks

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-punpklo-combine.ll:224
+declare <vscale x 4 x i1> @llvm.experimental.vector.extract.4x16(<vscale x 16 x i1>, i64)
+declare <vscale x 2 x i1> @llvm.experimental.vector.extract.2x16(<vscale x 16 x i1>, i64)
+
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I believe these should be spelled "v2i16", etc?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111221/new/

https://reviews.llvm.org/D111221