[PATCH] D115448: [AArch64][SVE] Instcombine SDIV to ASRD

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

To match the equivalent functionality in D113281 <https://reviews.llvm.org/D113281>, can you also add support for signed divides by negative powers or two?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115448/new/

https://reviews.llvm.org/D115448