[PATCH] D113798: Add loop unrolling and peeling preferences for RISCV

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

@luismarques and I were chatting about this patch some more. A few thoughts I'm writing down so we don't lose them (we should discuss on the call today too).

The key question is whether this unrolling should be enabled for all RISC-V targets or not. Looking at other backends:

- AArch64: more aggressive unrolling options only enabled for in-order models
- ARM: Most unrolling options only enabled for M-class cores

Is it your view that this transformation is worthwhile on all common RISC-V microarchitectures?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113798/new/

https://reviews.llvm.org/D113798