[PATCH] D108115: [DAG][sve] Lowering for VLS masked truncating stores

[David Truby via Phabricator via llvm-commits]

DavidTruby added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9843
+  // truncating store.  We can do this even if this is already a truncstore.
+  if ((Value.getOpcode() == ISD::FP_ROUND ||
+       Value.getOpcode() == ISD::TRUNCATE) &&
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paulwalker-arm wrote:
> This will fail once D114580 lands because that patch breaks the symmetry between truncating stores and masked truncating stores.  If we can drop the `ISD::FP_ROUND` part of the combine then great otherwise we either need to add support for floating point to this patch or wait for D112536.
I think for now we should land this without the FP_ROUND condition to get the code improvement in for LLVM 14 and then fix it up correctly in D112536 (which unfortunately needs a fair bit more work)


Repository:
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  https://reviews.llvm.org/D108115/new/

https://reviews.llvm.org/D108115