[llvm] d43c801 - [ARM] Peek through And 1 in IsCMPZCSINC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 8 07:40:29 PST 2021
Author: David Green
Date: 2021-12-08T15:40:23Z
New Revision: d43c801d136e2a0bf8002b82ab08c2bec08b3d74
URL: https://github.com/llvm/llvm-project/commit/d43c801d136e2a0bf8002b82ab08c2bec08b3d74
DIFF: https://github.com/llvm/llvm-project/commit/d43c801d136e2a0bf8002b82ab08c2bec08b3d74.diff
LOG: [ARM] Peek through And 1 in IsCMPZCSINC
We can be in situations where And 1 zext nodes will not have been yet,
preventing us from detecting removable cmpz/csinc patterns. This peeks
through those nodes allowing us to simplify more code.
Differential Revision: https://reviews.llvm.org/D115176
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/Thumb2/active_lane_mask.ll
llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
llvm/test/CodeGen/Thumb2/mve-pred-and.ll
llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
llvm/test/CodeGen/Thumb2/mve-pred-not.ll
llvm/test/CodeGen/Thumb2/mve-pred-or.ll
llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
llvm/test/CodeGen/Thumb2/mve-pred-spill.ll
llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
llvm/test/CodeGen/Thumb2/mve-selectcc.ll
llvm/test/CodeGen/Thumb2/mve-vcmp.ll
llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 3281451581e15..eb4ce54529790 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -14636,6 +14636,15 @@ static SDValue IsCMPZCSINC(SDNode *Cmp, ARMCC::CondCodes &CC) {
if (Cmp->getOpcode() != ARMISD::CMPZ || !isNullConstant(Cmp->getOperand(1)))
return SDValue();
SDValue CSInc = Cmp->getOperand(0);
+
+ // Ignore any `And 1` nodes that may not yet have been removed. We are
+ // looking for a value that produces 1/0, so these have no effect on the
+ // code.
+ while (CSInc.getOpcode() == ISD::AND &&
+ isa<ConstantSDNode>(CSInc.getOperand(1)) &&
+ CSInc.getConstantOperandVal(1) == 1 && CSInc->hasOneUse())
+ CSInc = CSInc.getOperand(0);
+
if (CSInc.getOpcode() != ARMISD::CSINC ||
!isNullConstant(CSInc.getOperand(0)) ||
!isNullConstant(CSInc.getOperand(1)) || !CSInc->hasOneUse())
diff --git a/llvm/test/CodeGen/Thumb2/active_lane_mask.ll b/llvm/test/CodeGen/Thumb2/active_lane_mask.ll
index 02f2a871117d4..74df7be81241d 100644
--- a/llvm/test/CodeGen/Thumb2/active_lane_mask.ll
+++ b/llvm/test/CodeGen/Thumb2/active_lane_mask.ll
@@ -4,57 +4,53 @@
define <2 x i64> @v2i64(i32 %index, i32 %TC, <2 x i64> %V1, <2 x i64> %V2) {
; CHECK-LABEL: v2i64:
; CHECK: @ %bb.0:
-; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov q0[2], q0[0], r0, r0
; CHECK-NEXT: vmov.i64 q1, #0xffffffff
; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vmov q2[2], q2[0], r1, r1
; CHECK-NEXT: vmov r0, r12, d1
+; CHECK-NEXT: vmov lr, s0
; CHECK-NEXT: adds r0, #1
-; CHECK-NEXT: adc lr, r12, #0
-; CHECK-NEXT: vmov r12, s0
-; CHECK-NEXT: vmov q0[2], q0[0], r12, r0
+; CHECK-NEXT: vmov q0[2], q0[0], lr, r0
+; CHECK-NEXT: adc r12, r12, #0
; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vmov r4, r5, d1
; CHECK-NEXT: vldr d1, [sp, #16]
-; CHECK-NEXT: vmov r1, r6, d3
; CHECK-NEXT: eors r0, r4
+; CHECK-NEXT: orrs.w r0, r0, r12
+; CHECK-NEXT: vmov r1, r0, d3
+; CHECK-NEXT: cset r12, eq
; CHECK-NEXT: subs r1, r4, r1
-; CHECK-NEXT: sbcs.w r1, r5, r6
-; CHECK-NEXT: vmov r5, r4, d2
-; CHECK-NEXT: cset r1, lo
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: orrs.w r0, r0, lr
-; CHECK-NEXT: cset r0, eq
+; CHECK-NEXT: sbcs.w r0, r5, r0
+; CHECK-NEXT: vmov r1, r5, d0
+; CHECK-NEXT: cset r0, lo
+; CHECK-NEXT: vmov d0, r2, r3
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: cset r0, ne
+; CHECK-NEXT: and.w r0, r0, r12
+; CHECK-NEXT: rsb.w r12, r0, #0
+; CHECK-NEXT: vmov r4, r0, d2
+; CHECK-NEXT: subs r4, r1, r4
+; CHECK-NEXT: sbcs.w r0, r5, r0
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r0, ne
+; CHECK-NEXT: teq.w r1, lr
+; CHECK-NEXT: cset r1, eq
; CHECK-NEXT: ands r0, r1
-; CHECK-NEXT: vmov r1, r6, d0
+; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: vmov d0, r2, r3
-; CHECK-NEXT: subs r5, r1, r5
-; CHECK-NEXT: sbcs r6, r4
-; CHECK-NEXT: cset r6, lo
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: cset r6, ne
-; CHECK-NEXT: teq.w r1, r12
-; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: cset r1, ne
-; CHECK-NEXT: ands r1, r6
-; CHECK-NEXT: movs r6, #0
-; CHECK-NEXT: rsbs r1, r1, #0
-; CHECK-NEXT: bfi r6, r1, #0, #8
-; CHECK-NEXT: bfi r6, r0, #8, #8
+; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: add r0, sp, #24
+; CHECK-NEXT: bfi r1, r12, #8, #8
; CHECK-NEXT: vldrw.u32 q1, [r0]
-; CHECK-NEXT: vmsr p0, r6
+; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vmov r2, r3, d1
-; CHECK-NEXT: pop {r4, r5, r6, pc}
+; CHECK-NEXT: pop {r4, r5, r7, pc}
%active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC)
%select = select <2 x i1> %active.lane.mask, <2 x i64> %V1, <2 x i64> %V2
ret <2 x i64> %select
diff --git a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
index 02b95b078ab6b..403e60e9dfd56 100644
--- a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
@@ -330,8 +330,10 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: ext_ops_trunc_i32:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r10, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r10, lr}
+; CHECK-NEXT: .pad #4
+; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s8, s4
@@ -347,7 +349,6 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: vand q1, q1, q3
; CHECK-NEXT: vmov.f32 s2, s3
-; CHECK-NEXT: vmov r9, s0
; CHECK-NEXT: adds r4, r3, r1
; CHECK-NEXT: asr.w r6, r3, #31
; CHECK-NEXT: adc.w r5, r6, r0
@@ -373,77 +374,71 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
; CHECK-NEXT: orr.w r7, r7, r3, asr #31
; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: cset r7, eq
-; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: csetm r7, ne
+; CHECK-NEXT: csetm r7, eq
; CHECK-NEXT: bfi r4, r7, #0, #8
; CHECK-NEXT: eor.w r7, r0, r2
; CHECK-NEXT: orr.w r7, r7, r0, asr #31
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: cset r7, eq
-; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: csetm r7, ne
+; CHECK-NEXT: csetm r7, eq
; CHECK-NEXT: bfi r4, r7, #8, #8
-; CHECK-NEXT: asr.w r7, r9, #31
; CHECK-NEXT: vmsr p0, r4
; CHECK-NEXT: rsbs r4, r3, #0
; CHECK-NEXT: mla r3, lr, r2, r8
; CHECK-NEXT: lsll r10, r5, r4
; CHECK-NEXT: lsll r10, r5, r1
; CHECK-NEXT: lsll r6, r3, r0
+; CHECK-NEXT: vmov r0, r7, d3
; CHECK-NEXT: lsll r6, r3, r2
+; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov q4[2], q4[0], r10, r6
; CHECK-NEXT: vmov q4[3], q4[1], r5, r3
; CHECK-NEXT: vmov r1, r3, d2
-; CHECK-NEXT: vmov r0, r5, d3
; CHECK-NEXT: vpsel q2, q4, q2
; CHECK-NEXT: vmov.f32 s9, s10
-; CHECK-NEXT: adds.w r6, r9, r1
-; CHECK-NEXT: adcs r7, r3
-; CHECK-NEXT: asrl r6, r7, r1
-; CHECK-NEXT: subs.w r8, r6, r1
-; CHECK-NEXT: vmov r6, s2
-; CHECK-NEXT: sbc.w lr, r7, r3
-; CHECK-NEXT: umull r2, r7, r8, r1
-; CHECK-NEXT: adds r4, r6, r0
-; CHECK-NEXT: asr.w r3, r6, #31
-; CHECK-NEXT: adcs r3, r5
+; CHECK-NEXT: asrs r6, r2, #31
+; CHECK-NEXT: adds r4, r2, r1
+; CHECK-NEXT: adc.w r5, r6, r3
+; CHECK-NEXT: asrl r4, r5, r1
+; CHECK-NEXT: subs r6, r4, r1
+; CHECK-NEXT: sbc.w lr, r5, r3
+; CHECK-NEXT: vmov r5, s2
+; CHECK-NEXT: adds r4, r5, r0
+; CHECK-NEXT: asr.w r3, r5, #31
+; CHECK-NEXT: adcs r3, r7
; CHECK-NEXT: asrl r4, r3, r0
; CHECK-NEXT: subs r4, r4, r0
-; CHECK-NEXT: sbcs r3, r5
-; CHECK-NEXT: umull r4, r5, r4, r0
-; CHECK-NEXT: mla r3, r3, r0, r5
-; CHECK-NEXT: eor.w r5, r9, r1
-; CHECK-NEXT: orr.w r5, r5, r9, asr #31
-; CHECK-NEXT: cmp r5, #0
-; CHECK-NEXT: cset r5, eq
-; CHECK-NEXT: cmp r5, #0
-; CHECK-NEXT: csetm r5, ne
-; CHECK-NEXT: bfi r12, r5, #0, #8
-; CHECK-NEXT: eor.w r5, r6, r0
-; CHECK-NEXT: orr.w r5, r5, r6, asr #31
-; CHECK-NEXT: rsbs r6, r6, #0
-; CHECK-NEXT: cmp r5, #0
-; CHECK-NEXT: lsll r4, r3, r6
-; CHECK-NEXT: cset r5, eq
-; CHECK-NEXT: lsll r4, r3, r0
-; CHECK-NEXT: cmp r5, #0
-; CHECK-NEXT: rsb.w r0, r9, #0
-; CHECK-NEXT: csetm r5, ne
-; CHECK-NEXT: bfi r12, r5, #8, #8
-; CHECK-NEXT: mla r5, lr, r1, r7
+; CHECK-NEXT: sbcs r3, r7
+; CHECK-NEXT: umull r4, r7, r4, r0
+; CHECK-NEXT: mla r3, r3, r0, r7
+; CHECK-NEXT: eor.w r7, r2, r1
+; CHECK-NEXT: orr.w r7, r7, r2, asr #31
+; CHECK-NEXT: cmp r7, #0
+; CHECK-NEXT: csetm r7, eq
+; CHECK-NEXT: bfi r12, r7, #0, #8
+; CHECK-NEXT: eor.w r7, r5, r0
+; CHECK-NEXT: orr.w r7, r7, r5, asr #31
+; CHECK-NEXT: cmp r7, #0
+; CHECK-NEXT: csetm r7, eq
+; CHECK-NEXT: bfi r12, r7, #8, #8
+; CHECK-NEXT: umull r6, r7, r6, r1
; CHECK-NEXT: vmsr p0, r12
-; CHECK-NEXT: lsll r2, r5, r0
-; CHECK-NEXT: lsll r2, r5, r1
-; CHECK-NEXT: vmov q0[2], q0[0], r2, r4
+; CHECK-NEXT: rsb.w r12, r5, #0
+; CHECK-NEXT: lsll r4, r3, r12
+; CHECK-NEXT: mla r5, lr, r1, r7
+; CHECK-NEXT: lsll r4, r3, r0
+; CHECK-NEXT: rsbs r0, r2, #0
+; CHECK-NEXT: lsll r6, r5, r0
+; CHECK-NEXT: lsll r6, r5, r1
+; CHECK-NEXT: vmov q0[2], q0[0], r6, r4
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov.f32 s10, s0
; CHECK-NEXT: vmov.f32 s11, s2
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vpop {d8, d9}
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
+; CHECK-NEXT: add sp, #4
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r10, pc}
entry:
%sa = sext <4 x i32> %a to <4 x i64>
%sb = zext <4 x i32> %b to <4 x i64>
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-and.ll b/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
index 2d62ba9b86b5b..e745fafdbea72 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
@@ -578,15 +578,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: vmov r0, r1, d4
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, r2, d5
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
@@ -609,13 +605,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r12, r2, d5
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: ands r0, r1
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: rsbs r0, r0, #0
@@ -626,12 +618,8 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r2
; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: ands r0, r2
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #8, #8
@@ -653,15 +641,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
; CHECK-NEXT: eors r3, r1
; CHECK-NEXT: eors r2, r0
; CHECK-NEXT: orrs r2, r3
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov r3, r2, d0
-; CHECK-NEXT: cset r12, ne
+; CHECK-NEXT: cset r12, eq
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: mov.w r3, #0
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: and.w r2, r2, r12
; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: bfi r3, r2, #0, #8
@@ -671,12 +655,8 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: ands r0, r1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r3, r0, #8, #8
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll b/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
index 13afb8ef602bd..470007878ec84 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
@@ -367,16 +367,12 @@ define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) {
; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: vmov r0, r1, d0
; CHECK-LE-NEXT: orrs r0, r1
-; CHECK-LE-NEXT: cset r0, eq
-; CHECK-LE-NEXT: cmp r0, #0
-; CHECK-LE-NEXT: mov.w r0, #0
-; CHECK-LE-NEXT: csetm r1, ne
+; CHECK-LE-NEXT: csetm r1, eq
+; CHECK-LE-NEXT: movs r0, #0
; CHECK-LE-NEXT: bfi r0, r1, #0, #1
; CHECK-LE-NEXT: vmov r1, r2, d1
; CHECK-LE-NEXT: orrs r1, r2
-; CHECK-LE-NEXT: cset r1, eq
-; CHECK-LE-NEXT: cmp r1, #0
-; CHECK-LE-NEXT: csetm r1, ne
+; CHECK-LE-NEXT: csetm r1, eq
; CHECK-LE-NEXT: bfi r0, r1, #1, #1
; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: bx lr
@@ -388,16 +384,12 @@ define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) {
; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: vmov r0, r1, d3
; CHECK-BE-NEXT: orrs r0, r1
-; CHECK-BE-NEXT: cset r0, eq
-; CHECK-BE-NEXT: cmp r0, #0
-; CHECK-BE-NEXT: mov.w r0, #0
-; CHECK-BE-NEXT: csetm r1, ne
+; CHECK-BE-NEXT: csetm r1, eq
+; CHECK-BE-NEXT: movs r0, #0
; CHECK-BE-NEXT: bfi r0, r1, #0, #1
; CHECK-BE-NEXT: vmov r1, r2, d2
; CHECK-BE-NEXT: orrs r1, r2
-; CHECK-BE-NEXT: cset r1, eq
-; CHECK-BE-NEXT: cmp r1, #0
-; CHECK-BE-NEXT: csetm r1, ne
+; CHECK-BE-NEXT: csetm r1, eq
; CHECK-BE-NEXT: bfi r0, r1, #1, #1
; CHECK-BE-NEXT: add sp, #4
; CHECK-BE-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll b/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
index 82ba80a2e9282..e39614efd680b 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
@@ -330,15 +330,11 @@ define arm_aapcs_vfpcc void @store_v2i1(<2 x i1> *%dst, <2 x i64> %a) {
; CHECK-LE-NEXT: vmov r1, r2, d0
; CHECK-LE-NEXT: orrs r1, r2
; CHECK-LE-NEXT: mov.w r2, #0
-; CHECK-LE-NEXT: cset r1, eq
-; CHECK-LE-NEXT: cmp r1, #0
-; CHECK-LE-NEXT: csetm r1, ne
+; CHECK-LE-NEXT: csetm r1, eq
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
; CHECK-LE-NEXT: vmov r1, r3, d1
; CHECK-LE-NEXT: orrs r1, r3
-; CHECK-LE-NEXT: cset r1, eq
-; CHECK-LE-NEXT: cmp r1, #0
-; CHECK-LE-NEXT: csetm r1, ne
+; CHECK-LE-NEXT: csetm r1, eq
; CHECK-LE-NEXT: bfi r2, r1, #1, #1
; CHECK-LE-NEXT: strb r2, [r0]
; CHECK-LE-NEXT: bx lr
@@ -349,15 +345,11 @@ define arm_aapcs_vfpcc void @store_v2i1(<2 x i1> *%dst, <2 x i64> %a) {
; CHECK-BE-NEXT: vmov r1, r2, d3
; CHECK-BE-NEXT: orrs r1, r2
; CHECK-BE-NEXT: mov.w r2, #0
-; CHECK-BE-NEXT: cset r1, eq
-; CHECK-BE-NEXT: cmp r1, #0
-; CHECK-BE-NEXT: csetm r1, ne
+; CHECK-BE-NEXT: csetm r1, eq
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
; CHECK-BE-NEXT: vmov r1, r3, d2
; CHECK-BE-NEXT: orrs r1, r3
-; CHECK-BE-NEXT: cset r1, eq
-; CHECK-BE-NEXT: cmp r1, #0
-; CHECK-BE-NEXT: csetm r1, ne
+; CHECK-BE-NEXT: csetm r1, eq
; CHECK-BE-NEXT: bfi r2, r1, #1, #1
; CHECK-BE-NEXT: strb r2, [r0]
; CHECK-BE-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-not.ll b/llvm/test/CodeGen/Thumb2/mve-pred-not.ll
index b21129b33b1b9..16bb6c4672648 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-not.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-not.ll
@@ -326,15 +326,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, r2, d1
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q1, q0
@@ -352,15 +348,11 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, r2, d1
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q1, q0
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-or.ll b/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
index dd38d0d154ed1..2310e380de1cf 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-or.ll
@@ -383,8 +383,6 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #1
@@ -397,8 +395,6 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r2, #1
@@ -425,8 +421,6 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r12, r2, d5
; CHECK-NEXT: cset r1, eq
@@ -442,8 +436,6 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r2
; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: cmp r2, #0
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll b/llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
index 37ad04e3609e9..307d93eca112f 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
@@ -6,14 +6,10 @@ define <2 x i64> @shuffle1_v2i64(<2 x i64> %src, <2 x i64> %a, <2 x i64> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: mov.w r3, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r3, r0, #8, #8
; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: vldrw.u32 q0, [r0]
@@ -111,14 +107,10 @@ define <2 x i64> @shuffle2_v2i64(<2 x i64> %src, <2 x i64> %a, <2 x i64> %b) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: orrs.w r0, r2, r3
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: vldrw.u32 q0, [r0]
@@ -203,9 +195,7 @@ define <2 x i64> @shuffle3_v2i64(<2 x i64> %src, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: shuffle3_v2i64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: vldrw.u32 q0, [r0]
@@ -307,9 +297,7 @@ define <2 x i64> @shuffle4_v2i64(<2 x i64> %src, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: shuffle4_v2i64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: orrs.w r0, r2, r3
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: vldrw.u32 q0, [r0]
@@ -617,28 +605,20 @@ define <4 x i32> @shuffle6_v2i64(<2 x i64> %src1, <2 x i64> %src2, <4 x i32> %a,
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #4
; CHECK-NEXT: orrs.w r0, r2, r3
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #4, #4
; CHECK-NEXT: mov r0, sp
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vmov r0, r2, d0
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #4
; CHECK-NEXT: vmov r0, r2, d1
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #12, #4
; CHECK-NEXT: add r0, sp, #32
; CHECK-NEXT: vldrw.u32 q0, [r0]
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll b/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll
index ad593659daaf1..3bc129d0fd92e 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll
@@ -20,16 +20,12 @@ define arm_aapcs_vfpcc <2 x i64> @shuffle1_v2i64(<2 x i64> %src, <2 x i64> %a) {
; CHECK-LE-NEXT: vmov q4, q1
; CHECK-LE-NEXT: orrs r0, r1
; CHECK-LE-NEXT: mov.w r1, #0
-; CHECK-LE-NEXT: cset r0, eq
-; CHECK-LE-NEXT: cmp r0, #0
-; CHECK-LE-NEXT: csetm r0, ne
+; CHECK-LE-NEXT: csetm r0, eq
; CHECK-LE-NEXT: bfi r1, r0, #0, #8
; CHECK-LE-NEXT: vmov r0, r2, d1
; CHECK-LE-NEXT: vmov.i32 q0, #0x0
; CHECK-LE-NEXT: orrs r0, r2
-; CHECK-LE-NEXT: cset r0, eq
-; CHECK-LE-NEXT: cmp r0, #0
-; CHECK-LE-NEXT: csetm r0, ne
+; CHECK-LE-NEXT: csetm r0, eq
; CHECK-LE-NEXT: bfi r1, r0, #8, #8
; CHECK-LE-NEXT: vmsr p0, r1
; CHECK-LE-NEXT: vpsel q0, q1, q0
@@ -55,15 +51,11 @@ define arm_aapcs_vfpcc <2 x i64> @shuffle1_v2i64(<2 x i64> %src, <2 x i64> %a) {
; CHECK-BE-NEXT: vmov.i32 q0, #0x0
; CHECK-BE-NEXT: orrs r0, r1
; CHECK-BE-NEXT: mov.w r1, #0
-; CHECK-BE-NEXT: cset r0, eq
-; CHECK-BE-NEXT: cmp r0, #0
-; CHECK-BE-NEXT: csetm r0, ne
+; CHECK-BE-NEXT: csetm r0, eq
; CHECK-BE-NEXT: bfi r1, r0, #0, #8
; CHECK-BE-NEXT: vmov r0, r2, d3
; CHECK-BE-NEXT: orrs r0, r2
-; CHECK-BE-NEXT: cset r0, eq
-; CHECK-BE-NEXT: cmp r0, #0
-; CHECK-BE-NEXT: csetm r0, ne
+; CHECK-BE-NEXT: csetm r0, eq
; CHECK-BE-NEXT: bfi r1, r0, #8, #8
; CHECK-BE-NEXT: vmsr p0, r1
; CHECK-BE-NEXT: vpsel q0, q4, q0
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll b/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
index 63ddd40056742..b53b1d969cc9d 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
@@ -77,12 +77,8 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, r3, d2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r0, r1, r2, ne
; CHECK-NEXT: movs r1, #0
@@ -95,12 +91,8 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: vmov r3, r0, d3
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: orrs r0, r3
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r2, r0, ne
; CHECK-NEXT: rsbs r0, r0, #0
@@ -397,24 +389,16 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1_i1(<2 x i64> %a, <2 x i64> %b, i64
; CHECK-NEXT: vmov r0, r1, d2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r3, d3
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: csetm r12, ne
+; CHECK-NEXT: csetm r12, eq
+; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: orrs r1, r3
-; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov r1, r3, d0
-; CHECK-NEXT: csetm lr, ne
+; CHECK-NEXT: csetm lr, eq
; CHECK-NEXT: orrs r1, r3
-; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov r1, r4, d1
-; CHECK-NEXT: csetm r3, ne
+; CHECK-NEXT: csetm r3, eq
; CHECK-NEXT: orrs r1, r4
-; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csetm r1, ne
+; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: cbz r2, .LBB15_2
; CHECK-NEXT: @ %bb.1: @ %select.false
; CHECK-NEXT: bfi r0, r12, #0, #8
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll b/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
index 04027ed0c5407..8741b2b70554d 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
@@ -463,8 +463,6 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: eorne r1, r1, #1
@@ -477,8 +475,6 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: eorne r2, r2, #1
@@ -505,8 +501,6 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r12, r2, d5
; CHECK-NEXT: cset r1, eq
@@ -522,8 +516,6 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: orrs r0, r2
; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: cmp r2, #0
diff --git a/llvm/test/CodeGen/Thumb2/mve-selectcc.ll b/llvm/test/CodeGen/Thumb2/mve-selectcc.ll
index 22e5edc948118..c4a71f1429ae2 100644
--- a/llvm/test/CodeGen/Thumb2/mve-selectcc.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-selectcc.ll
@@ -217,9 +217,7 @@ define i32 @e() {
; CHECK-NEXT: adds r0, #4
; CHECK-NEXT: vadd.i32 q2, q2, q1
; CHECK-NEXT: cmp r0, #8
-; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csetm r1, ne
+; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: subs.w r2, r0, #8
; CHECK-NEXT: vdup.32 q3, r1
; CHECK-NEXT: csel r0, r0, r2, ne
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmp.ll b/llvm/test/CodeGen/Thumb2/mve-vcmp.ll
index e1af135199f91..fae8e393ea949 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmp.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmp.ll
@@ -373,18 +373,14 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, <2 x i64> %srcb,
; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: vmov r12, r2, d3
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r3, r0, d1
; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: eor.w r2, r3, r12
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q2, q3
@@ -433,18 +429,14 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, <2 x i64> %srcb,
; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: vmov r12, r2, d3
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r3, r0, d1
; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: eor.w r2, r3, r12
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q2, q3
@@ -461,18 +453,14 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: csetm r1, ne
+; CHECK-NEXT: csetm r1, eq
+; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: bfi r2, r1, #0, #8
; CHECK-NEXT: vmov r1, r3, d1
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: orrs r1, r3
; CHECK-NEXT: vmov r3, s8
-; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csetm r1, ne
+; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: bfi r2, r1, #8, #8
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: vpsel q0, q0, q2
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
index 43bdc2cc46215..9b765e8ac938b 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
@@ -438,17 +438,13 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x
; CHECK-NEXT: eors r2, r0
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: mov.w r3, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r12, r2, d1
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: eor.w r0, r0, r12
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r3, r0, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q1, q2
@@ -469,17 +465,13 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x
; CHECK-NEXT: eors r2, r0
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: mov.w r3, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r12, r2, d1
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: eor.w r0, r0, r12
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r3, r0, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q1, q2
@@ -498,18 +490,14 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: csetm r1, ne
+; CHECK-NEXT: csetm r1, eq
+; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: bfi r2, r1, #0, #8
; CHECK-NEXT: vmov r1, r3, d1
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: orrs r1, r3
; CHECK-NEXT: vmov r3, s8
-; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csetm r1, ne
+; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: bfi r2, r1, #8, #8
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: vpsel q0, q0, q2
@@ -999,17 +987,13 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eq_v2i64(<2 x i64> %src, i64 %src2, <2
; CHECK-NEXT: eors r2, r0
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: mov.w r3, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r12, r2, d1
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: eor.w r0, r0, r12
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r3, r0, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q1, q2
@@ -1030,17 +1014,13 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eq_v2i32(<2 x i64> %src, i64 %src2, <2
; CHECK-NEXT: eors r2, r0
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: mov.w r3, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r12, r2, d1
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: eor.w r0, r0, r12
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r3, r0, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q1, q2
@@ -1059,18 +1039,14 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b,
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov.w r0, #0
-; CHECK-NEXT: csetm r1, ne
+; CHECK-NEXT: csetm r1, eq
+; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: bfi r2, r1, #0, #8
; CHECK-NEXT: vmov r1, r3, d1
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: orrs r1, r3
; CHECK-NEXT: vmov r3, s8
-; CHECK-NEXT: cset r1, eq
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csetm r1, ne
+; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: bfi r2, r1, #8, #8
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: vpsel q0, q0, q2
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
index 8f4905e6b7358..fcb9d136307fe 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
@@ -364,15 +364,11 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eqz_v2i64(<2 x i64> %src, <2 x i64> %a, <
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, r2, d1
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q1, q2
@@ -389,15 +385,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eqz_v2i32(<2 x i64> %src, <2 x i32> %a, <
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, r2, d1
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q1, q2
@@ -774,15 +766,11 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eqz_v2i64(<2 x i64> %src, <2 x i64> %a,
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, r2, d1
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q1, q2
@@ -799,15 +787,11 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eqz_v2i32(<2 x i64> %src, <2 x i32> %a,
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, r2, d1
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q1, q2
diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
index 9297b11216e42..f9948db66b3b3 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
@@ -50,16 +50,12 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_zext(<2 x i32> %x, <2 x i32> %b) {
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
@@ -88,16 +84,12 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x, <2 x i32> %b) {
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
@@ -426,16 +418,12 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_zext(<2 x i16> %x, <2 x i16> %b) {
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
@@ -460,16 +448,12 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_sext(<2 x i16> %x, <2 x i16> %b) {
; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmsr p0, r1
@@ -1354,16 +1338,12 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_zext(<2 x i8> %x, <2 x i8> %b) {
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
@@ -1388,16 +1368,12 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_sext(<2 x i8> %x, <2 x i8> %b) {
; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmsr p0, r1
@@ -1428,16 +1404,12 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x, <2 x i64> %b) {
; CHECK-NEXT: vmov r0, r1, d2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, r2, d3
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
@@ -1507,16 +1479,12 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_zext(<2 x i32> %x, <2 x i32> %b,
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q0, q1
@@ -1550,16 +1518,12 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_sext(<2 x i32> %x, <2 x i32> %b,
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q0, q1
@@ -1876,16 +1840,12 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_zext(<2 x i16> %x, <2 x i16> %b,
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q0, q1
@@ -1915,16 +1875,12 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_sext(<2 x i16> %x, <2 x i16> %b,
; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmsr p0, r3
@@ -2558,16 +2514,12 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_zext(<2 x i8> %x, <2 x i8> %b, i6
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q0, q1
@@ -2597,16 +2549,12 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_sext(<2 x i8> %x, <2 x i8> %b, i6
; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmsr p0, r3
@@ -2642,16 +2590,12 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, <2 x i64> %b, i64
; CHECK-NEXT: vmov r2, r3, d2
; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: orrs r2, r3
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r12, r2, #0, #8
; CHECK-NEXT: vmov r2, r3, d3
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: orrs r2, r3
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r12, r2, #8, #8
; CHECK-NEXT: vmsr p0, r12
; CHECK-NEXT: vpsel q0, q0, q1
diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
index 17a638dfd51f0..63b1431ac0fa4 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
@@ -55,15 +55,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_zext(<2 x i32> %x, <2 x i32> %y, <2
; CHECK-NEXT: vmullb.u32 q3, q0, q1
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q3, q0
@@ -90,15 +86,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x, <2 x i32> %y, <2
; CHECK-NEXT: vmullb.s32 q3, q0, q1
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q3, q0
@@ -374,16 +366,12 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_zext(<2 x i16> %x, <2 x i16> %y, <2
; CHECK-NEXT: vmov q0[3], q0[1], r3, r1
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
@@ -413,17 +401,13 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_sext(<2 x i16> %x, <2 x i16> %y, <2
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: sxth r2, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: sxth r3, r3
-; CHECK-NEXT: csetm r0, ne
-; CHECK-NEXT: smull r2, r3, r3, r2
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s10
+; CHECK-NEXT: sxth r3, r3
+; CHECK-NEXT: smull r2, r3, r3, r2
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmsr p0, r1
@@ -1576,16 +1560,12 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_zext(<2 x i8> %x, <2 x i8> %y, <2 x i
; CHECK-NEXT: vmov q0[3], q0[1], r3, r1
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
@@ -1615,17 +1595,13 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_sext(<2 x i8> %x, <2 x i8> %y, <2 x i
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: sxtb r2, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: sxtb r3, r3
-; CHECK-NEXT: csetm r0, ne
-; CHECK-NEXT: smull r2, r3, r3, r2
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, s10
+; CHECK-NEXT: sxtb r3, r3
+; CHECK-NEXT: smull r2, r3, r3, r2
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmsr p0, r1
@@ -1673,15 +1649,11 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64
; CHECK-NEXT: vmov r0, r1, d4
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmov r0, r2, d5
; CHECK-NEXT: orrs r0, r2
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, ne
+; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
@@ -1757,15 +1729,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_zext(<2 x i32> %x, <2 x i32> %y,
; CHECK-NEXT: vmullb.u32 q3, q0, q1
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q3, q0
@@ -1797,15 +1765,11 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_sext(<2 x i32> %x, <2 x i32> %y,
; CHECK-NEXT: vmullb.s32 q3, q0, q1
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q3, q0
@@ -2024,16 +1988,12 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_zext(<2 x i16> %x, <2 x i16> %y,
; CHECK-NEXT: vmov q0[3], q0[1], r3, r12
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q0, q1
@@ -2065,15 +2025,11 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_sext(<2 x i16> %x, <2 x i16> %y,
; CHECK-NEXT: vand q2, q2, q3
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmsr p0, r3
@@ -2927,16 +2883,12 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_zext(<2 x i8> %x, <2 x i8> %y, <2
; CHECK-NEXT: vmov q0[3], q0[1], r3, r12
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q0, q1
@@ -2968,15 +2920,11 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_sext(<2 x i8> %x, <2 x i8> %y, <2
; CHECK-NEXT: vand q2, q2, q3
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmsr p0, r3
@@ -3032,15 +2980,11 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, <2 x i64> %y, <2 x
; CHECK-NEXT: vmov r2, r3, d4
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: mov.w r3, #0
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
; CHECK-NEXT: vmov r2, r7, d5
; CHECK-NEXT: orrs r2, r7
-; CHECK-NEXT: cset r2, eq
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csetm r2, ne
+; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpsel q0, q0, q1
diff --git a/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll b/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
index 624a05f736c02..726237eb27f2d 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
@@ -283,15 +283,11 @@ define arm_aapcs_vfpcc <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64>
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: cmp.w r1, #-1
-; CHECK-NEXT: cset r1, gt
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csetm r1, ne
+; CHECK-NEXT: csetm r1, gt
; CHECK-NEXT: bfi r0, r1, #0, #8
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: cmp.w r1, #-1
-; CHECK-NEXT: cset r1, gt
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csetm r1, ne
+; CHECK-NEXT: csetm r1, gt
; CHECK-NEXT: bfi r0, r1, #8, #8
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q1, q2
More information about the llvm-commits
mailing list