[PATCH] D115259: [AArch64][SVE] Lower vector.insert to predicated SEL

Wed Dec 8 07:02:31 PST 2021

peterwaller-arm added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/split-vector-insert.ll:17
+; CHECK-LEGALIZATION-NEXT:    addvl sp, sp, #-3
+; CHECK-LEGALIZATION-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
+; CHECK-LEGALIZATION-NEXT:    .cfi_offset w29, -16
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You've run update_llc_test_checks on this file, which did not previously use it but the intent of the test was not to check the output-- it was checking for 'legally typed node' in the debug output. I think you can keep the newer CHECK lines but this diff hunk needs discarding.

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Comment at: llvm/test/CodeGen/AArch64/split-vector-insert.ll:139
+; CHECK-LEGALIZATION-NEXT:    ret
+;
 ; CHECK-LABEL: test_nxv2f64_v8f64:
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Same for this one.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115259/new/

https://reviews.llvm.org/D115259