[PATCH] D114960: [AArch64][SVE] Lower shuffles to permute instructions: rev/revb/revh/revw

[weiwei via Phabricator via llvm-commits]

wwei added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19322-19323
+        RevOp = AArch64ISD::REVW_MERGE_PASSTHRU;
+      Op = LowerToPredicatedOp(DAG.getNode(ISD::BITCAST, DL, NewVT, Op1), DAG,
+                               RevOp);
+      Op = DAG.getNode(ISD::BITCAST, DL, ContainerVT, Op);
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paulwalker-arm wrote:
> Calling `LowerToPredicatedOp` feels like overkill here compared to `DAG.getNode(RevOp, DL, NewVT, ..., DAG.getUNDEF(NewVT)`
Since there's no unpredicated `revb/revh/revw` for SVE, `LowerToPredicatedOp` can help to construct a predicate operand, and can handle merge passthru opcode also. If using `DAG.getNode(RevOp, DL, NewVT, ..., DAG.getUNDEF(NewVT)`, we need some extra code to get a predicate operand and pass correct merge passthru operands.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114960/new/

https://reviews.llvm.org/D114960