[PATCH] D115310: [RISCV] Use MULHU for more division by constant cases.

[Craig Topper via Phabricator via llvm-commits]

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D113805 <https://reviews.llvm.org/D113805> improved handling of i32 divu/remu on RV64. The basic idea
from that can be extended to (mul (and X, C2), C1 <https://reviews.llvm.org/C1>) where C2 is any
mask constant.

We can replace the and with an SLLI by shifting by the number of
leading zeros in C2 if we also shift C1 <https://reviews.llvm.org/C1> left by XLen - lzcnt(C1 <https://reviews.llvm.org/C1>)
bits. This will give the full product XLen additional trailing zeros,
putting the result in the output of MULHU. If we can't use ANDI,
ZEXT.H, or ZEXT.W, this will avoid materializing C2 in a register.

The downside is it make take 1 additional instruction to create C1 <https://reviews.llvm.org/C1>.
But since that's not on the critical path, it can hopefully be
interleaved with other operations.

The previous tablegen pattern is replaced by custom isel code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115310

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoM.td
  llvm/test/CodeGen/RISCV/div.ll
  llvm/test/CodeGen/RISCV/pr51206.ll
  llvm/test/CodeGen/RISCV/urem-lkk.ll
  llvm/test/CodeGen/RISCV/xaluo.ll

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